Complementary cascoded logic circuit

Claim 2

A high switching speed low power logical circuit for performing a logical function, said logical circuit comprising: input circuit means, said input circuit means having at least first and second input terminals and reduced capacitance; a first transistor having a collector, base and emitter, said base of said first transistor connected to said input circuit means; a first resistor connected between said base of said first transistor and a first source of potential; a second resistor connected between said collector of said first transistor and said first source of potential; active current source means connected between said emitter of said first transistor and a second source of potential, said active current source means including the serial interconnection of a diode and an inversely operated transistor, said inversely operated transistor having a collector, base and emitter, said collector of said inversely operated transistor connected to said input circuit means and to a second potential source; circuit means including a reference source of potential connected between said base of said inversely operated transistor and said collector of said first transistor; a second transistor having a collector base and emitter, said collector of said second transistor connected to said first source of potential, said base of said second transistor connected to said collector of said first transistor; a third resistor serially connected between the emitter of said second transistor and said second potential source; and an output terminal connected to said emitter of said second transistor.

Claim 3

A high switching speed low power logical circuit for performing a logical function, as recited in claim 1, wherein said input circuit means includes at least first and second PNP type transistors, each of said PNP type transistors having a collector, base and emitter, said emitters of said PNP type transistors connected in common to said base of said first transistor, said collectors of said first and second PNP type transistors connected in common to said collector of said inversely operated transistor, said bases of said first and second PNP type transistors respectively connected to said first and second input terminals, and wherein said first transistor, said inversely operated transistor and said second transistor are respectively NPN type transistors.

Claim 4

A high switching speed low power logical circuit for performing a logical function, as recited in claim 2, wherein said active current source means includes a low voltage Schottky diode having an anode and a cathode and an inversely operated NPN type transistor, said anode of said Schottky diode connected to said emitter of said first transistor, said cathode of said Schottky diode connected to said emitter of said inversely operated transistor.

Claim 5

A high switching speed low power logical circuit for performing a logical function, as recited in claim 3, wherein said circuit means including a source of reference potential includes first and second low voltage Schottky diodes, said anode of said first Schottky diode connected to said collector of said first NPN transistor, said cathode of said second Schottky diode connected to said collector of said first NPN transistor, and a resistor connected between said base of said inversely operated transistor and a common connection of said cathode of said first Schottky diode and said anode of said second Schottky diode.

Claim 6

A high switching speed low power logical circuit for performing a logical function, as recited in claim 4, wherein said active current source means includes a speed-up capacitor connected between said emitter of said first transistor and said collector of said inversely operated transistor.

Claim 7

Logic circuit means employing active redundancy, said logic circuit means comprising: at least first, second, third, fourth, fifth, and sixth logic circuits; said first and said second logic circuits each having at least one input and an output; said third logic circuit having a first input, a second input and an output, said first input of said third logic circuit connected to said output of said first logic circuit, said second input of said third logic circuit connected to said output of said second logic circuit; said fourth logic circuit having a first input, a second input and an output, said first input of said fourth logic circuit connected to said output of said first logic circuit, said second input of said fourth logic circuit connected to said output of said second logic circuit; said fifth logic circuit having a first input, a second input and an output, said first input of said fifth logic circuit connected to said output of said third logic circuit, said second input of said fifth logic circuit connected to said output of said fourth logic circuit; said sixth logic circuit having a first input, a second input and an output, said first input of said sixth logic circuit connected to said output of said third logic circuit, said second input of said sixth logic circuit connected to said output of said fourth logic circuit; and said logic circuit means being further characterized by each of said first through sixth logic circuits being a complementary cascoded logic (C 2 L) circuit, wherein each complementary cascoded logic (C 2 L) circuit comprises: input circuit means, said input circuit means having at least first and second input terminals and reduced capacitance; a first transistor having a collector, base and emitter, said base of said first transistor connected to said input circuit means; a first resistor connected between said base of said first transistor and a first source of potential; a second resistor connected between said collector of said first transistor and said first source of potential; active current source means connected between said emitter of said first transistor and a second source of potential, said active current source means including the serial interconnection of a diode and an inversely operated transistor, said inversely operated transistor having a collector, base and emitter, said collector of said inversely operated transistor connected to said input circuit means and to a second potential source; circuit means including a reference source of potential connected between said base of said inversely operated transistor and said collector of said first transistor; a second transistor having a collector, base and emitter, said collector of said second transistor connected to said first source of potential, said base of said second transistor connected to said collector of said first transistor; a third resistor serially connected between the emitter of said second transistor and said second potential source; and an output terminal connected to said emitter of said second transistor, whereby said circuit means is capable of obviating at least certain defects or faults in at least one of said first through sixth complementary cascoded logic circuits.

Claim 8

Logic circuit means employing active redundancy, said logic circuit means comprising: at least first, second, third, fourth, fifth, and sixth logic circuits; said first and said second logic circuits each having at least one input and an output; said third logic circuit having a first input, a second input and an output, said first input of said third logic circuit connected to said output of said first logic circuit, said second input of said third logic circuit connected to said output of said second logic circuit; said fourth logic circuit having a first input, a second input and an output, said first input of said fourth logic circuit connected to said output of said first logic circuit, said second input of said fourth logic circuit connected to said output of said second logic circuit; said fifth logic circuit having a first input, a second input and an output, said first input of said fifth logic circuit connected to said output of said third logic circuit, said second input of said fifth logic circuit connected to said output of said fourth logic circuit; said sixth logic circuit having a first input, a second input and an output, said first input of said sixth logic circuit connected to said output of said third logic circuit, said second input of said sixth logic circuit connected to said output of said fourth logic circuit; and said logic circuit means being further characterized by each of said first through sixth logic circuits being a complementary cascoded logic (C 2 L) circuit, wherein each complementary cascoded logic (C 2 L) circuit comprises: input circuit means, said input circuit means having at least first and second input terminals and reduced capacitance; a first transistor having a collector, base and emitter, said base of said first transistor connected to said input circuit means; a first resistor connected between said base of said first transistor and a first source of potential; a second resistor connected between said collector of said first transistor and said first source of potential; active current source means connected between said emitter of said first transistor and a second source of potential, said active current source means including the serial interconnection of a diode and an inversely operated transistor, said inversely operated transistor having a collector, base and emitter, said collector of said inversely operated transistor connected to said input circuit means and to a second potential source; circuit means including a reference source of potential connected between said base of said inversely operated transistor and said collector of said first transistor; a second transistor having a collector, base and emitter, said collector of said second transistor connected to said first source of potential, said base of said second transistor connected to said collector of said first transistor; a third resistor serially connected between the emitter of said second transistor and said second potential source; and an output terminal connected to said emitter of said second transistor, whereby said circuit means is capable of obviating at least certain defects or faults in at least one of said first through sixth complementary cascoded logic circuits.

Claim 9

Logic circuit means employing active redundancy, as recited in claim 6, wherein said input circuit means includes at least first and second PNP type transistors, each of said PNP type transistors having a collector, base and emitter, said emitters of said PNP type transistors connected in common to said base of said first transistor, said collectors of said first and second PNP type transistors connected in common to said collector of said inversely operated transistor, said bases of said first and second PNP type transistors respectively connected to said first and second input terminals, and wherein said first transistor, said inversely operated transistor and said second transistor are respectively NPN type transistors.

Claim 10

Logic circuit means employing active redundancy, as recited in claim 7, wherein said active current source means includes a low voltage Schottky diode having an anode and a cathode and an inversely operated NPN type transistor, said anode of said Schottky diode connected to said emitter of said first transistor, said cathode of said Schottky diode connected to said emitter of said inversely operated transistor.

Claim 11

Logic circuit means employing active redundancy, as recited in claim 8, wherein said circuit means including a source of reference potential includes first and second low voltage Schottky diodes, said anode of said first Schottky diode connected to said collector of said first NPN transistor, said cathode of said second Schottky diode connected to said collector of said first NPN transistor, and a resistor connected between said base of said inversely operated transistor and a common connection of said cathode of said first Schottky diode and said anode of said second Schottky diode.

Claim 12

Logic circuit means employing active redundancy, as recited in claim 9, wherein said active current source means includes a speed-up capacitor connected between said emitter of said first transistor and said collector of said inversely operated transistor.

Claim 13

A high switching speed low power logical circuit for performing a logical function, said logical circuit comprising: input circuit means, said input circuit means having at least first and second input terminals and reduced capacitance; a first transistor having a collector, base and emitter, said base of said first transistor connected to said input circuit means; a first resistor connected between said base of said first transistor and a first source of potential; a second resistor connected between said collector of said first transistor and said first source of potential; active current source means connected between said emitter of said first transistor and a second source of potential, said active current source means including the serial interconnection of a diode and an inversely operated transistor; and, output circuit means coupled to said input circuit means and said active current source means.

Claim 14

A high switching speed low power logical circuit for performing a logical function, said logical circuit comprising: input circuit means, said input circuit means having at least first and second input terminals and reduced capacitance; a first transistor having a collector, base and emitter, said base of said first transistor connected to said input circuit means; a first resistor connected between said base of said first transistor and a first source of potential; a second resistor connected between said collector of said first transistor and said first source of potential; active current source means connected between said emitter of said first transistor and a second source of potential, said active current source means including the serial interconnection of a diode and an inversely operated transistor; and, output circuit means coupled to said input circuit means and said active current source means.

Claim 15

A high switching speed low power logical circuit for performing a logical function, said logical circuit comprising: input circuit means, said input circuit means including at least first and second input terminals; output circuit means, said output circuit means including an output terminal; and, circuit means coupling said input circuit means to said output circuit means, said logic circuit being characterized in that said circuit means coupling said input circuit means to said output circuit means includes an active current source means consisting essentially of the serial interconnection of a diode and an inversely operated transistor.

Claim 16

A high switching speed low power logical circuit for performing a logical function, said logical circuit comprising: input circuit means, said input circuit means including at least first and second input terminals; output circuit means, said output circuit means including an output terminal; and, circuit means coupling said input circuit means to said output circuit means, said logic circuit being characterized in that said circuit means coupling said input circuit means to said output circuit means includes an active current source means consisting essentially of the serial interconnection of a diode and an inversely operated transistor.

Claim 17

Logic circuit means employing active redundancy, said logic circuit means comprising: at least first, second, third and fourth logic circuits; said first and second logic circuits each having at least one input and an output; said third logic circuit having a first input, a second input and an output, said first input of said third logic circuit connected to said output of said first logic circuit, said second input of said third logic circuit connected to said output of said second logic circuit; said fourth logic circuit having a first input, a second input and an output, said first input of said fourth logic circuit connected to said output of said first logic circuit, said second input of said fourth logic circuit connected to said output of said second logic circuit; said logic circuit means being characterized by each of said first through fourth logic circuits being a complementary cascoded logic (C 2 L), wherein each complementary cascoded logic (C 2 L) circuit comprises: input circuit means, said input circuit means having at least first and second input terminals and reduced capacitance; a first transistor having a collector, base and emitter, said base of said first transistor connected to said input circuit means; a first resistor connected between said base of said first transistor and a first source of potential; a second resistor connected between said collector of said first transistor and said first source of potential; active current source means connected between said emitter of said first transistor and a second source of potential, said active current source means including the serial interconnection of a diode and an inversely operated transistor, said inversely operated transistor having a collector, base and emitter, said collector of said inversely operated transistor connected to said input circuit means and to a second potential source; circuit means including a reference source of potential connected between said base of said inversely operated transistor and said collector of said first transistor; a second transistor having a collector, base and emitter, said collector of said second transistor connected to said first source of potential, said base of said second transistor connected to said collector of said first transistor; a third resistor serially connected between the emitter of said second transistor and said second potential source; and an output terminal connected to said emitter of said second transistor; whereby said circuit means is capable of obviating at least certain defects or faults in at least one of said first through fourth complementary cascoded logic circuits.

Claim 18

Logic circuit means employing active redundancy, said logic circuit means comprising: at least first, second, third and fourth logic circuits; said first and second logic circuits each having at least one input and an output; said third logic circuit having a first input, a second input and an output, said first input of said third logic circuit connected to said output of said first logic circuit, said second input of said third logic circuit connected to said output of said second logic circuit; said fourth logic circuit having a first input, a second input and an output, said first input of said fourth logic circuit connected to said output of said first logic circuit, said second input of said fourth logic circuit connected to said output of said second logic circuit; said logic circuit means being characterized by each of said first through fourth logic circuits being a complementary cascoded logic (C 2 L), wherein each complementary cascoded logic (C 2 L) circuit comprises: input circuit means, said input circuit means having at least first and second input terminals and reduced capacitance; a first transistor having a collector, base and emitter, said base of said first transistor connected to said input circuit means; a first resistor connected between said base of said first transistor and a first source of potential; a second resistor connected between said collector of said first transistor and said first source of potential; active current source means connected between said emitter of said first transistor and a second source of potential, said active current source means including the serial interconnection of a diode and an inversely operated transistor, said inversely operated transistor having a collector, base and emitter, said collector of said inversely operated transistor connected to said input circuit means and to a second potential source; circuit means including a reference source of potential connected between said base of said inversely operated transistor and said collector of said first transistor; a second transistor having a collector, base and emitter, said collector of said second transistor connected to said first source of potential, said base of said second transistor connected to said collector of said first transistor; a third resistor serially connected between the emitter of said second transistor and said second potential source; and an output terminal connected to said emitter of said second transistor; whereby said circuit means is capable of obviating at least certain defects or faults in at least one of said first through fourth complementary cascoded logic circuits.

Claim 19

Logic circuit means employing active redundancy, as recited in claim 13, wherein said input circuit means includes at least first and second PNP type transistors, each of said PNP type transistors having a collector, base and emitter, said emitters of said PNP type transistors connected in common to said base of said first transistor, said collectors of said first and second PNP type transistors connected in common to said collector of said inversely operated transistor, said bases of said first and second PNP type transistors respectively connected to said first and second input terminals, and wherein said first transistor, said inversely operated transistor and said second transistor are respectively NPN type transistors.

Claim 20

Logic circuit means employing active redundancy, as recited in claim 14, wherein said active current source means includes a low voltage Schottky diode having an anode and a cathode and an inversely operated NPN type transistor, said anode of said Schottky diode connected to said emitter of said first transistor, said cathode of said Schottky diode connected to said emitter of said inversely operated transistor.

Claim 21

Logic circuit means employing active redundancy, as recited in claim 15, wherein said circuit means including a source of reference potential includes first and second low voltage Schottky diodes, said anode of said first Schottky diode connected to said collector of said first NPN transistor, said cathode of said second Schottky diode connected to said collector of said first NPN transistor, and a resistor connected between said base of said inversely operated transistor and a common connection of said cathode of said first Schottky diode and said anode of said second Schottky diode.

Claim 22

Logic circuit means employing active redundancy, as recited in claim 16, wherein said active current source means includes a speed-up capacitor connected between said emitter of said first transistor and said collector of said inversely operated transistor.