US3579272A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic circuits
Assignee: Plessey Overseas Ltd
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Filing: 1969-02-12
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Granted: 1971-05-18
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Expires: 1989-02-12
Abstract
Abstract An emitter coupled logic circuit comprises a long-tailed pair switch defined by transistors connected respectively to output transistors in emitter follower configuration. A VBE variation with temperature of said output transistors being compensated for by further transistors whose bases are provided with a constant voltage supply.
Inventors
- 👤 Richard Charles Foss
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:54
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
163 words
An emitter coupled logic circuit comprising a long-taileD pair current switch defined by two transistors having load components connected to their respective collectors, current stabilizing means connected to the emitters of said transistors, an emitter follower connected transistor the base of which is connected to the collector of one of the said two transistors, and a compensation transistor having similar electrical characteristics to said emitter follower connected transistor, the collector of said compensation transistor being connected to the collector of the said one of the said two transistors so that when in operation of said logic circuit a stable voltage is applied to the base of said compensation transistor, a current is drawn through the load component connected to the collector of the said one of the said two transistors which is dependent on temperature and which is of a magnitude such as to compensate for the voltage changes with temperature across the base-emitter junction of the transistor which forms the emitter follower.
Claim 2
Dependent Claim
163 words
An emitter coupled logic circuit comprising a long-taileD pair current switch defined by two transistors having load components connected to their respective collectors, current stabilizing means connected to the emitters of said transistors, an emitter follower connected transistor the base of which is connected to the collector of one of the said two transistors, and a compensation transistor having similar electrical characteristics to said emitter follower connected transistor, the collector of said compensation transistor being connected to the collector of the said one of the said two transistors so that when in operation of said logic circuit a stable voltage is applied to the base of said compensation transistor, a current is drawn through the load component connected to the collector of the said one of the said two transistors which is dependent on temperature and which is of a magnitude such as to compensate for the voltage changes with temperature across the base-emitter junction of the transistor which forms the emitter follower.
Claim 3
Dependent Claim
37 words
An emitter coupled logic circuit as claimed in claim 1 including voltage stabilizing means to which the base of the said one of the said two transistors and the base of the said compensation transistor is connected.
Claim 4
Dependent Claim
85 words
An emitter coupled logic circuit as claimed in claim 2, wherein the current stabilizing means which is connected to provide a constant current in the tail of said transistor long-tailed pair comprises a transistor herein called a stabilizing transistor the collector of which is connected to the emitters of the said pair, the emitter of the stabilizing transistor being connected through a resistor to one supply rail and the base of the stabilizing transistor being supplied with a substantially constant voltage from voltage stabilizing means.
Claim 5
Dependent Claim
30 words
An emitter coupled logic circuit as claimed in claim 1 comprising a clamping circuit for limiting at least one logic level afforded by the said circuit to a predetermined level.
Claim 6
Dependent Claim
33 words
An emitter coupled logic circuit as claimed in claim 4, wherein the clamping circuit includes temperature compensating means such that the logic level clamped is substantially constant in the presence of temperature variations.
Claim 7
Dependent Claim
120 words
An emitter coupled logic circuit as claimed in claim 4 wherein the clamping circuit comprises a first transistor the emitter of which is connected to a load component of the current switch, the base of said first transistor being connected at a junction formed between one end of the first resistor and the collector of a second transistor, the base of which is connected to a reference voltage and the emitter of which is connected to one end of a second resistor, the collector of said first transistor and the other end of the first resistor being connected to one supply rail and the other end of the second resistor being connected to one supply another opposite polarity supply rail.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-17 | 1974-11-16 | 1975-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-17 | 1978-11-16 | 1979-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-17 | 1982-11-16 | 1983-05-18 | $7700.00 | Window Closed / Lapsed |