High speed/logic circuit

Claim 1

A high speed logic circuit, comprising: a number of unit logic gates, each of said unit logic gates comprising, a number of gate transistors having input terminals for receiving logic signals having a first logic level and a second logic level at their base electrodes and output terminals connected with their collector electrodes, a collector series resistor interconnecting said collector electrodes with the first terminal of a voltage source and an emitter series resistor interconnecting the emitter electrodes of said gate transistors with the second terminal of said voltage source, said collector series resistor having a resistance value higher than the sum of said emitter series resistance value and the incremental emitter junction resistance value of said gate transistors with an input signal exceeding the base-to-emitter voltage of said gate transistors applied to at least one of said input terminals; said voltage source having a voltage such that when said input signal is at said first logic level the voltage difference between said at least one input terminal and said second terminal of the voltage source is insufficient for the at least one of said gate transistors to which said input signal is applied to be switched to an active state from a non-conducting state and the collector current of said gate transistors being limited by said emitter series resistor when said input signal is at said second logic level so that the collector junction of said at least one gate transistor does not inject minority carriers; wherein the potential difference between said voltage source terminals is defined by the formulas V1 - V2 < VBEI + VL VL < VBEI - VCES wherein V1 is the voltage at said first voltage source terminal and V2 is the voltage at said second voltage source terminal, VBEI is the base to emitter forward voltage of said gate transistors, VL is the logic swing of said gate transistors, VCES is the collector-emitter saturation voltage of said gate transistors and wherein said collector series resistor and said emitter series resistor are defined by 1 < RC/RE + re < VBEI VCES/V1 - V2 - VBEI wherein RC and RE are said collector and emitter series resistors, respectively, and re is said incremental emitter junction resistance value; and wherein said high speed logic circuit is formed by directly coupling the output terminals of each of said logic gates to the input terminals of other of said logic gates whereby the signal levels at each of said input and output terminals of each of said logic gates are maintained at substantially constant binary values.