US3560770A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Temperature correction of a logic circuit arrangement
Assignee: US Philips Corp
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Filing: 1967-12-27
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Granted: 1971-02-02
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Expires: 1987-12-27
Abstract
Abstract A temperature compensated logic circuit having two transistors with commonly connected emitters and a third transistor, the collector-emitter path of which connects the emitters of the two transistors through a resistance to one terminal of a two terminal source of supply. A voltage divider having two taps is connected between the terminals, one tap being connected to the base electrode of one of the two emitter-connected transistors. The temperature compensation is through a barrier layer connecting the base electrode of the third transistor to the other divider tap, while a resistance further connects the base electrode of the third transistor to the other supply terminal.
Inventors
- 👤 Joannes Paulus Maria Gieles
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 00:05
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
163 words
A temperature-compensated logic circuit arrangement comprising first, second and third transistors, said first and second transistors having their respective emitters connected to each other and through the series circuit of the collectoremitter junction of said third transistor and an emitter-resistor to a first terminal of a two-terminal source of supply, means connecting the collectors of said first and second transistors to the second terminal of said two-terminal source of supply, a voltage divider connected between said two terminals and having two taps, the base of one of said first and second transistors being coupled to one of said taps, a barrier layer connecting the base of the third transistor to the other of said voltage divider taps, said barrier layer having the same pass direction as that of the base-emitter junction of said third transistor, when viewed from the base of said third transistor, and a resistor connecting the base of the third transistor to said second terminal of said source of supply.
Claim 2
Dependent Claim
163 words
A temperature-compensated logic circuit arrangement comprising first, second and third transistors, said first and second transistors having their respective emitters connected to each other and through the series circuit of the collectoremitter junction of said third transistor and an emitter-resistor to a first terminal of a two-terminal source of supply, means connecting the collectors of said first and second transistors to the second terminal of said two-terminal source of supply, a voltage divider connected between said two terminals and having two taps, the base of one of said first and second transistors being coupled to one of said taps, a barrier layer connecting the base of the third transistor to the other of said voltage divider taps, said barrier layer having the same pass direction as that of the base-emitter junction of said third transistor, when viewed from the base of said third transistor, and a resistor connecting the base of the third transistor to said second terminal of said source of supply.
Claim 3
Dependent Claim
45 words
A circuit arrangement as claimed in claim 1, wherein said barrier layer constitutes the emitter-base junction of a fourth transistor which is complementary to said third transistor, and means connecting the collector of said fourth transistor to the first terminal of said source of supply.
Claim 4
Dependent Claim
43 words
The combination of claim 2, wherein said last named means includes a fifth transistor having its base connected to the collector of said fourth transistor, its collector connected to the emitter of said fourth transistor, and its emitter connected to said first terminal.
References Cited (Backward Citations)
US3046487A
Cited
US3182269A
Cited
US3310688A
Cited
US3431508A
Cited
US3419810A
Cited
US3414834A
Cited
US3435362A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-01 | 1974-08-03 | 1975-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-01 | 1978-08-03 | 1979-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-01 | 1982-08-03 | 1983-02-02 | $7700.00 | Window Closed / Lapsed |