Method of making thin film field effect transistors for a liquid crystal display device

Claim 1

A method for the manufacture of at least one coplanar thin film field effect transistor with self-alignment of the electrodes, wherein the method comprises the eight following successive stages: first stage: successively depositing on a substrate a semiconductor coating and a gate insulant coating, second stage: defining mesas by a first set of resin masks and etching the resulting exposed semiconductor and gate insulant coatings down to the level of the substrate, to form mesas on the substrate, each of the mesas serving to form a transistor, third stage: depositing a passivation insulant coating on the substrate and the resin masks and exposing the gate insulant by removing the passivation insulant down to the level of the gate insulant and removing the resin mask, fourth stage: depositing an electrode layer on the passivation and gate insulant layers and forming gate electrodes by depositing a second set of resin masks over a portion of the gate insulant and removing the remaining electrode layer, fifth stage: etching the gate insulant coating not covered by the gate electrodes until the semiconductor coating is exposed, sixth stage: forming source and drain regions by ion implantation, seventh stage: eliminating the second resin masks, followed by activation of the ions implanted in the preceding stage, eighth stage: forming a third set of resin masks over the gate electrode and depositing source and drain electrode layers on the structure obtained in the previous stage and removing the third resin and the electrode layer thereon to form source and drain electrodes.

Claim 2

A method for the manufacture of at least one coplanar thin film field effect transistor with self-alignment of the electrodes, wherein the method comprises the eight following successive stages: first stage: successively depositing on a substrate a semiconductor coating and a gate insulant coating, second stage: defining mesas by a first set of resin masks and etching the resulting exposed semiconductor and gate insulant coatings down to the level of the substrate, to form mesas on the substrate, each of the mesas serving to form a transistor, third stage: depositing a passivation insulant coating on the substrate and the resin masks and exposing the gate insulant by removing the passivation insulant down to the level of the gate insulant and removing the resin mask, fourth stage: depositing an electrode layer on the passivation and gate insulant layers and forming gate electrodes by depositing a second set of resin masks over a portion of the gate insulant and removing the remaining electrode layer, fifth stage: etching the gate insulant coating not covered by the gate electrodes until the semiconductor coating is exposed, sixth stage: forming source and drain regions by ion implantation, seventh stage: eliminating the second resin masks, followed by activation of the ions implanted in the preceding stage, eighth stage: forming a third set of resin masks over the gate electrode and depositing source and drain electrode layers on the structure obtained in the previous stage and removing the third resin and the electrode layer thereon to form source and drain electrodes.

Claim 13

A method for the manufacture of at least one coplanar thin film field effect transistor with self-alignment of the electrodes, wherein the method comprises the eight following successive stages: first stage: successively depositing on a substrate a semiconductor coating at a temperature which does not deteriorate the substrate and a gate insulant coating at a temperature that does not exceed the deposition temperature of said semiconductor coating, second stage: defining mesas by a first set of resin masks and etching the resulting exposed semiconductor and gate insulant coatings down to the level of the substrate, to form mesas on the substrate, each of the mesas serving to form a transistor, third stage: depositing a passivation insulant coating on the substrate and the resin masks and exposing the gate insulant by removing the passivation insulant down to the level of the gate insulant and removing the resin masks, fourth stage: depositing an electrode layer on the passivation and gate insulant layers and forming gate electrodes by depositing a second set of resin masks over a portion of the gate insulant and removing the remaining electrode layer, fifth stage: etching the gate insulant coating not covered by the gate electrodes until the semiconductor coating is exposed, sixth stage: forming source and drain regions by ion implantation, seventh stage: eliminating the second resin masks, followed by activation of the ions implanted in the preceding stage, eighth stage: forming a third set of resin masks over the gate electrode and depositing source and drain electrode layers on the structure obtained in the previous stage and removing the third resin and the electrode layer thereon to form source and drain electrodes.

Claim 14

A method for the manufacture of at least one coplanar thin film field effect transistor with self-alignment of the electrodes, wherein the method comprises the eight following successive stages: first stage: successively depositing on a substrate a semiconductor coating at a temperature which does not deteriorate the substrate and a gate insulant coating at a temperature that does not exceed the deposition temperature of said semiconductor coating, second stage: defining mesas by a first set of resin masks and etching the resulting exposed semiconductor and gate insulant coatings down to the level of the substrate, to form mesas on the substrate, each of the mesas serving to form a transistor, third stage: depositing a passivation insulant coating on the substrate and the resin masks and exposing the gate insulant by removing the passivation insulant down to the level of the gate insulant and removing the resin masks, fourth stage: depositing an electrode layer on the passivation and gate insulant layers and forming gate electrodes by depositing a second set of resin masks over a portion of the gate insulant and removing the remaining electrode layer, fifth stage: etching the gate insulant coating not covered by the gate electrodes until the semiconductor coating is exposed, sixth stage: forming source and drain regions by ion implantation, seventh stage: eliminating the second resin masks, followed by activation of the ions implanted in the preceding stage, eighth stage: forming a third set of resin masks over the gate electrode and depositing source and drain electrode layers on the structure obtained in the previous stage and removing the third resin and the electrode layer thereon to form source and drain electrodes.