Digital signal processing apparatus

Claim 2

A digital signal processing apparatus comprising: a first signal processing section including delay means for generating (2p+1) signals x k-n to x k+n (n=0, 1, 2, . . . , p) each having a different respective delay time and means responsive to said signals x k-n to x k+n for calculating a first output signal ##EQU11## wherein j and h 0 to h n are "±1" and "1" or "0", respectively; a second signal processing section responsive to said first output signal y k or said signal x k for calculating a second output signal in the same manner as said first signal processing section, said second signal processing section having the same construction as said first signal processing section; and means for delivering a third output signal from a center tap of the delay means of said second signal processing section, said second output signal and said third output signal being maintained in synchronism with one another.

Claim 3

A digital signal processing apparatus, comprising: a first signal processing section including first delay means for generating (2p+1) signals X k-n to X k+n (n=0, 1, 2, . . . , p) each having a different respective delay time, and means responsive to said signals X k-n to X k+n for calculating a first output signal ##EQU12## wherein j and h 0 to h n are "+1" and "1" or "0", respectively; a second signal processing section including second delay means receiving said first output signal Y 1 for generating (2p+1) signals Y 1k-n to Y 1k+n (n=0, 1, 2, . . . , p) each having a different respective delay time, and means responsive to said signals Y 1k-n to Y 1k+n for calculating a second output signal ##EQU13## wherein j and h 0 to h n are "±1" and "1" or "0", respectively; and signal delivering means for delivering a third output signal Y 1k from a center tap of said second delay means, said third output signal being in synchronism with said second output signal with respect to a delay time.

Claim 4

A digital signal processing apparatus, comprising: a first signal processing section including first delay means for generating (2p+1) signals X k-n to X k+n (n=0, 1, 2, . . . , p) each having a different respective delay time, and means responsive to said signals X k-n to X k+n for calculating a first output signal ##EQU12## wherein j and h 0 to h n are "+1" and "1" or "0", respectively; a second signal processing section including second delay means receiving said first output signal Y 1 for generating (2p+1) signals Y 1k-n to Y 1k+n (n=0, 1, 2, . . . , p) each having a different respective delay time, and means responsive to said signals Y 1k-n to Y 1k+n for calculating a second output signal ##EQU13## wherein j and h 0 to h n are "±1" and "1" or "0", respectively; and signal delivering means for delivering a third output signal Y 1k from a center tap of said second delay means, said third output signal being in synchronism with said second output signal with respect to a delay time.

Claim 5

A digital signal processing apparatus as in claim 2, wherein at least one of said first and second signal processing sections is a differentiating filter and wherein said h 0 and j are set to "0" and "-1", respectively.

Claim 6

A digital signal processing apparatus as in claim 2, wherein at least one of said first and second signal processing sections is a smoothing filter and wherein said coefficients j are set to "+1".

Claim 7

A digital signal processing apparatus as in claim 2, further comprising: a third signal processing section including third delay means receiving said signal X k from a center tap of said first delay means for generating (2p+1) signals X' k-n to X' k+n (n=0, 1, 2, . . . , p) each having a different respective delay time and means responsive to said signals X' k-n to X' k+n for calculating a fourth output signal ##EQU14## wherein j and h 0 to h n are "±1" and "1" or "0", respectively, whereby said fourth output signal Y 3 is in synchronism with said second and said third output signals.

Claim 8

A digital signal processing apparatus, comprising: delay means for generating (2p+1) signals x k-n to x k+n (n=0, 1, 2, . . . , p) each having a different respective time delay, said delay means being driven by a first clock signal which is generated as a function of a second clock signal, said second clock signal having a frequency which is at least twice the frequency of said first clock signal; designating means responsive to said second clock signal for sequentially designating a plurality of combinations of coefficients j and h 0 to h n during each cycle period of said first clock signal, said coefficients j and h 0 to h n being "±1" and "0" or "1", respectively; and computing means responsive to both (1) said signals x k-n to x k+n delivered from said delay means and (2) said combinations of cooefficients for computing, during each said cycle period of said first clock signal, a plurality of output signals ##EQU15##

Claim 9

A digital signal processing apparatus, comprising: delay means for generating (2p+1) signals x k-n to x k+n (n=0, 1, 2, . . . , p) each having a different respective time delay, said delay means being driven by a first clock signal which is generated as a function of a second clock signal, said second clock signal having a frequency which is at least twice the frequency of said first clock signal; designating means responsive to said second clock signal for sequentially designating a plurality of combinations of coefficients j and h 0 to h n during each cycle period of said first clock signal, said coefficients j and h 0 to h n being "±1" and "0" or "1", respectively; and computing means responsive to both (1) said signals x k-n to x k+n delivered from said delay means and (2) said combinations of cooefficients for computing, during each said cycle period of said first clock signal, a plurality of output signals ##EQU15##

Claim 10

A digital signal processing apparatus as in claim 6, wherein said designating means comprises a multiplexer which receives the plurality of said combinations of said coefficients j and h 0 to h n and which outputs one of the plurality of said combinations in response to said second clock signal, said second clock signal having a frequency which is equal to an integer multiple of said first clock signal.

Claim 11

A digital signal processing apparatus as in claim 7, further comprising signal delivering means for receiving said output signal y k computed in response to said second clock signal by said computing means for delivering a plurality of respective output signals in parallel.

Claim 12

A digital signal apparatus as in claim 6, wherein said designating means comprises a memory in which the plurality of said combinations of said coefficients j and h 0 to h n are pre-stored and which outputs one of the plurality of said combinations in response to a second clock signal, said second clock signal having a frequency which is equal to an integer multiple of said first clock signal.