Data modem clock extraction circuit

Claim 2

In a data modem receiver having means for converting an analog signal into a digital input signal, having a symbol rate, clock extraction apparatus comprising: a first filter means providing a periodic amplitude response and supplied with the digital input signal and providing successive outputs; a squaring circuit means for squaring each output of said filter means to provide a squared output signal containing a spectral component at the symbol rate.

Claim 3

The apparatus of claim 1 further including a phase-locked timing generator and a second filter means for filtering the squared output of said squaring circuit means to provide a clock error signal at symbol rate, such that the phase-locked timing generator is corrected at symbol rate.

Claim 4

In a data receiving apparatus including a sampling means for converting an analog received signal to a succession of digital samples at a selected sample rate higher than the symbol rate of said receiving apparatus, a method of clock extraction comprising the steps of: storing a plurality of said digital samples; calculating a plurality of quantities as the difference of respective said samples spaced a selected time interval apart; squaring each of said quantities to produce a plurality of squared quantities; forming a clock error signal as a sum and difference of selected squared quantities; and utilizing said clock error signal to generate a corrected clock signal.

Claim 5

In a data receiving apparatus including a sampling means for converting an analog received signal to a succession of digital samples at a selected sample rate higher than the symbol rate of said receiving apparatus, a method of clock extraction comprising the steps of: storing a plurality of said digital samples; calculating a plurality of quantities as the difference of respective said samples spaced a selected time interval apart; squaring each of said quantities to produce a plurality of squared quantities; forming a clock error signal as a sum and difference of selected squared quantities; and utilizing said clock error signal to generate a corrected clock signal.

Claim 6

The method of claim 3 wherein said step of calculating calculates said quantities according to the expression W n -W n-24 where W n-24 is a sample delayed by 24 samples from sample W n .

Claim 7

The method of claim 3 or 4 wherein the clock error is formed according to the expression D 0 2 -D 1 2 -D 2 2 +D 4 2 +D 5 2 -D 6 2 where D n 2 ,n=0 . . . 6 represents the said squared quantities with D o 2 being the most recently received said squared quantity and D 6 2 being the latest.

Claim 8

In a data receiver having sampling means for sampling an analog form of a received signal to produce a plurality of received signal samples at a sample rate, said sample rate being higher than the symbol rate of the data receiver, apparatus for use in correcting clock errors comprising: a double restrictive bandpass filter means having its filter characteristic located such that a peak thereof coincides with the frequency components of the received signal located at F c ±F o where F c is the carrier frequency and F o is one-half the symbol rate, said filter means being supplied with said samples at the sample rate and outputting a plurality of filtered quantities; means performing a nonlinear operation on the filtered quantities outputted by said filter means to provide an output signal containing a spectral component at the symbol rate.

Claim 9

In a data receiver having sampling means for sampling an analog form of a received signal to produce a plurality of received signal samples at a sample rate, said sample rate being higher than the symbol rate of the data receiver, apparatus for use in correcting clock errors comprising: a double restrictive bandpass filter means having its filter characteristic located such that a peak thereof coincides with the frequency components of the received signal located at F c ±F o where F c is the carrier frequency and F o is one-half the symbol rate, said filter means being supplied with said samples at the sample rate and outputting a plurality of filtered quantities; means performing a nonlinear operation on the filtered quantities outputted by said filter means to provide an output signal containing a spectral component at the symbol rate.

Claim 10

The apparatus of claim 6 further including a sampling filter means supplied with said output signal for filtering said output signal to provide a clock error correction signal.

Claim 11

The apparatus of claim 7 wherein said sampling filter means comprises a plurality of delay elements, selected outputs of which are multiplied by plus or minus "1" and summed to form said clock error correction signal.

Claim 14

In a data receiving apparatus including a sampling means supplied with an analog received signal and operative to convert said analog received signal to digital output samples at a selected sample rate higher than the symbol rate of said receiving apparatus, a method of clock extraction comprising the steps of: storing a plurality of samples of the output of the sampling means; calculating a plurality of first quantities as the difference of respective said samples spaced a selected time itnerval apart; performing a nonlinear operation on each of said first quantities to produce a plurality of second quantities containing a spectral component at the symbol rate; forming a clock error signal from selected said second quantities; and utilizing said clock error signal to generate a corrected clock signal.

Claim 15

In a data receiving apparatus including a sampling means supplied with an analog received signal and operative to convert said analog received signal to digital output samples at a selected sample rate higher than the symbol rate of said receiving apparatus, a method of clock extraction comprising the steps of: storing a plurality of samples of the output of the sampling means; calculating a plurality of first quantities as the difference of respective said samples spaced a selected time itnerval apart; performing a nonlinear operation on each of said first quantities to produce a plurality of second quantities containing a spectral component at the symbol rate; forming a clock error signal from selected said second quantities; and utilizing said clock error signal to generate a corrected clock signal.

Claim 16

The method of claim 11 wherein said step of calculating calculates said symbols according to the expression W n -W n-24 where W n-24 is a sample delayed 24 samples from sample W n .

Claim 17

The method of claim 11 or 12 wherein the clock error is calculated as a sum and difference of said second quantities.