Linear phase digital filter

Claim 2

Modem circuitry for processing digital signals, comprising means for providing a stream of said signals at a signal rate, means for sampling said signals at a sample rate higher than said signal rate to provide a sequence of samples, said means for sampling being connected to respond to said means for providing, means for filtering said samples, said means for filtering being connected to respond to said means for sampling, said means for filtering comprising means for storing at least N tap coefficients, where N is an integer, a first delay line for storing at least N consecutive said samples, a second delay line for storing at least one more sample than the number of said samples which can be stored in said first delay line, means for introducing a new one of said samples into one end of said first delay line, transferring an already stored sample from the other end of said first delay line to said second delay line, and shifting already stored samples in said first delay line and said second delay line in a particular direction, means for thereafter providing N successive pairs of said samples, each said pair having one member sample from each of said lines, by completely recirculating said first line in said particular direction, and separately and incompletely recirculating said second line in said particular direction, the successive samples provided from said first line being oppositely time ordered from the corresponding successive samples provided from said second line, means for producing, for each said pair, the product of the sum of said respective members and one of said tap coefficients, said means for producing being connected to respond to said means for recirculating, and accumulator means responsive to said means for producing and connected to accumulate said products to produce a filter output.

Claim 3

Modem circuitry for processing carrier signals modulated in accordance with digital data, comprising a digital discriminator for forming the respective products of successive values of said signals with earlier such values to produce a duty cycle modulated output representative of said data, and means for filtering said duty cycle modulated output, said means for filtering being connected to respond to said discriminator, said means for filtering comprising means for successively sampling said duty cycle modulated output to provide a sample stream, means for storing N tap coefficients, where N is an integer, a first delay line for storing at least N consecutive said samples, a second delay line for storing at least one more sample than the number of said samples which can be stored in said first delay line, means for introducing a new one of said samples into one end of said first delay line, transferring an already stored sample from the other end of said first delay line to said second delay line, and shifting already stored samples in said first delay line and said second delay line in a particular direction, means for thereafter providing N successive pairs of said samples, each said pair having one member sample from each of said lines, by completely recirculating said first line in said particular direction, and separately and incompletely recirculating said second line in said particular direction, the successive samples provided from said first line being oppositely time ordered from the corresponding successive samples provided from said second line, means for producing, for each said pair, the product of the sum of said respective members and one of said tap coefficients, said means for producing being connected to respond to said means for recirculating, and accumulator means responsive to said means for producing and connected to accumulate said products to produce a filter output.

Claim 4

Modem circuitry for processing carrier signals modulated in accordance with digital data, comprising a digital discriminator for forming the respective products of successive values of said signals with earlier such values to produce a duty cycle modulated output representative of said data, and means for filtering said duty cycle modulated output, said means for filtering being connected to respond to said discriminator, said means for filtering comprising means for successively sampling said duty cycle modulated output to provide a sample stream, means for storing N tap coefficients, where N is an integer, a first delay line for storing at least N consecutive said samples, a second delay line for storing at least one more sample than the number of said samples which can be stored in said first delay line, means for introducing a new one of said samples into one end of said first delay line, transferring an already stored sample from the other end of said first delay line to said second delay line, and shifting already stored samples in said first delay line and said second delay line in a particular direction, means for thereafter providing N successive pairs of said samples, each said pair having one member sample from each of said lines, by completely recirculating said first line in said particular direction, and separately and incompletely recirculating said second line in said particular direction, the successive samples provided from said first line being oppositely time ordered from the corresponding successive samples provided from said second line, means for producing, for each said pair, the product of the sum of said respective members and one of said tap coefficients, said means for producing being connected to respond to said means for recirculating, and accumulator means responsive to said means for producing and connected to accumulate said products to produce a filter output.

Claim 5

The modem circuitry of claims 1 or 2 further comprising control circuitry connected to cause, when an already stored sample is transferred from said first to said second line, the samples stored in said second line to move in a given direction, and to cause, during said recirculation of said second line, the samples stored in said second line to move in the same direction as said given direction.

Claim 6

The modem circuitry of claim 1 wherein said first delay line is N delay units in length and said second delay line comprises a first delay circuit N+1 delay units in length and a second delay circuit one delay unit in length.

Claim 7

The modem circuitry of claim 3 or 4 wherein said means for introducing, transferring and shifting comprises sampling clock means, data shift clock means, and multiplexer circuitry connected to respond to said sampling clock means and said data shift clock means, for introducing said new sample into one end of said first delay line and transferring said already stored sample from the other end of said first delay line to said second delay line, whenever said sampling clock means and said data shift clock means are simultaneously activated.

Claim 8

The modem circuitry of claim 5 wherein said means for thereafter separately recirculating comprises means for providing N activations of said data shift clock means.

Claim 9

The modem circuitry of claim 6 wherein said first delay line comprises an N-stage unidirectional shift register, said first delay circuit comprises an N+1-stage unidirectional shift register, and said second delay circuit comprises a single stage unidirectional shift register.

Claim 10

The modem circuitry of claim 4 or 7 wherein said means for transferring comprises means for moving said already stored sample to said one-unit delay circuit.

Claim 11

Modem circuitry for processing digital signals comprising means for processing said signals to form an output, and digital filter means connected to respond to said means for processing, for filtering said output, comprising means for sampling said output to provide a sample stream, said means for sampling being connected to respond to said digital filter means, means for storing N tap coefficients, means for storing at least the 2N most recent of said samples in time-ordered position, multiplication means, means for shifting said N most recent samples and said N tap coefficients to said multiplication means at a first clock rate, means for increasing the resolution of said filter, comprising means for shifting said 2N most recent samples to said multiplication means at a second clock rate, twice as fast as said first clock rate, whereby each of said tap coefficients is multiplied by two consecutive said samples, and means for selectively activating said means for increased resolution.

Claim 12

Modem circuitry for processing digital signals comprising means for processing said signals to form an output, and digital filter means connected to respond to said means for processing, for filtering said output, comprising means for sampling said output to provide a sample stream, said means for sampling being connected to respond to said digital filter means, means for storing N tap coefficients, means for storing at least the 2N most recent of said samples in time-ordered position, multiplication means, means for shifting said N most recent samples and said N tap coefficients to said multiplication means at a first clock rate, means for increasing the resolution of said filter, comprising means for shifting said 2N most recent samples to said multiplication means at a second clock rate, twice as fast as said first clock rate, whereby each of said tap coefficients is multiplied by two consecutive said samples, and means for selectively activating said means for increased resolution.

Claim 13

Modem circuitry for processing digital signals, comprising means for providing a stream of said signals at a signal rate, means for sampling said signals at a sample rate higher than said signal rate to provide a sequence of samples, said means for sampling being connected to respond to said means for providing, means for filtering said samples, said means for filtering being connected to respond to said means for sampling, said means for filtering comprising means for storing at least N tap coefficients, where N is an integer, a first delay line for storing N consecutive said samples, a second delay line for storing N+2 consecutive said samples, said second delay line comprising a first delay circuit N+1 delay units in length and a second delay circuit one delay unit in length, means for introducing a new one of said samples into one end of said first delay line and transferring an already stored sample from the other end of said first delay line to said second delay line, means for thereafter separately recirculating said samples stored in said first and second lines to provide N successive pairs of said samples, each said pair having one member sample from each of said lines, the relative directions of recirculation of said lines being such that the sequence of member samples drawn from one line is oppositely time ordered from the sequence of member samples drawn from the other line, means for producing, for each said pair, the product of the sum of said respective members and one of said tap coefficients, said means for producing being connected to respond to said means for recirculating, and accumulator means responsive to said means for producing and connected to accumulate said products to produce a filter output.

Claim 14

Modem circuitry for processing digital signals, comprising means for providing a stream of said signals at a signal rate, means for sampling said signals at a sample rate higher than said signal rate to provide a sequence of samples, said means for sampling being connected to respond to said means for providing, means for filtering said samples, said means for filtering being connected to respond to said means for sampling, said means for filtering comprising means for storing at least N tap coefficients, where N is an integer, a first delay line for storing N consecutive said samples, a second delay line for storing N+2 consecutive said samples, said second delay line comprising a first delay circuit N+1 delay units in length and a second delay circuit one delay unit in length, means for introducing a new one of said samples into one end of said first delay line and transferring an already stored sample from the other end of said first delay line to said second delay line, means for thereafter separately recirculating said samples stored in said first and second lines to provide N successive pairs of said samples, each said pair having one member sample from each of said lines, the relative directions of recirculation of said lines being such that the sequence of member samples drawn from one line is oppositely time ordered from the sequence of member samples drawn from the other line, means for producing, for each said pair, the product of the sum of said respective members and one of said tap coefficients, said means for producing being connected to respond to said means for recirculating, and accumulator means responsive to said means for producing and connected to accumulate said products to produce a filter output.

Claim 15

Modem circuitry for processing carrier signals modulated in accordance with digital data, comprising a digital discriminator for forming the respective products of successive values of said signals with earlier such values to produce a duty cycle modulated output representative of said data, and means for filtering said duty cycle modulated output, said means for filtering being connected to respond to said discriminator, said means for filtering comprising means for successively sampling said duty cycle modulated output to provide a sample stream, means for storing N tap coefficients, where N is an integer, a first delay line for storing N consecutive said samples, a second delay line for storing N+2 consecutive said samples, said second delay comprising a first delay circuit N+1 delay units in length and a second delay circuit one delay unit in length means for introducing a new one of said samples into one end of said first delay line and transferring an already stored sample from the other end of said first delay line to said second delay line, means for thereafter separately recirculating said samples stored in said first and second lines to provide N successive pairs of said samples, each said pair having one member sample from each of said lines, the relative directions of recirculation of said lines being such that the sequence of member samples drawn from one line is oppositely time ordered from the sequence of member samples drawn from the other line, means for producing, for each said pair, the product of the sum of said respective members and one of said tap coefficients, said means for producing being connected to respond to said means for recirculating, and accumulator means responsive to said means for producing and connected to accumulate said products to produce a filter output.

Claim 16

Modem circuitry for processing carrier signals modulated in accordance with digital data, comprising a digital discriminator for forming the respective products of successive values of said signals with earlier such values to produce a duty cycle modulated output representative of said data, and means for filtering said duty cycle modulated output, said means for filtering being connected to respond to said discriminator, said means for filtering comprising means for successively sampling said duty cycle modulated output to provide a sample stream, means for storing N tap coefficients, where N is an integer, a first delay line for storing N consecutive said samples, a second delay line for storing N+2 consecutive said samples, said second delay comprising a first delay circuit N+1 delay units in length and a second delay circuit one delay unit in length means for introducing a new one of said samples into one end of said first delay line and transferring an already stored sample from the other end of said first delay line to said second delay line, means for thereafter separately recirculating said samples stored in said first and second lines to provide N successive pairs of said samples, each said pair having one member sample from each of said lines, the relative directions of recirculation of said lines being such that the sequence of member samples drawn from one line is oppositely time ordered from the sequence of member samples drawn from the other line, means for producing, for each said pair, the product of the sum of said respective members and one of said tap coefficients, said means for producing being connected to respond to said means for recirculating, and accumulator means responsive to said means for producing and connected to accumulate said products to produce a filter output.

Claim 17

The modem circuitry of claim 2 wherein said first delay line is N delay units in length and second delay line comprises a first delay circuit N+1 delay units in length and a second delay circuit one delay unit in length.