Digital signal separation filters

Claim 2

A digital filter for separating signals occupying separate frequency portions of a contiguous range of input signal frequencies, comprising: a source of input signal; delaying means, including a shift register coupled to said source and having a plurality of signal taps including a center tap;

Claim 3

respective signal weighting means, coupled to ones of said signal taps, including a center tap weighting means, for weighting signals occurring at said taps; means, coupled to said signal weighting means, excluding said center tap weighting means for producing at a first output port a signal which is a sum of tap-weighted signals; first signal combining means having a first input coupled to receive said sum of tap-weighted signals and a second input coupled to said center tap weighting means for combining applied signals in a first sense to produce output signals occupying a relatively high frequency portion of said contiguous frequency range; and second signal combining means having a first input coupled to receive said sum of tap-weighted signals and a second input coupled to said center tap weighting means for combining applied signals in a second sense to produce output signals occupying a relatively low frequency portion of said contiguous frequency range, wherein the frequency responses of said first and second signal combining means are completely transfer functions.

Claim 4

respective signal weighting means, coupled to ones of said signal taps, including a center tap weighting means, for weighting signals occurring at said taps; means, coupled to said signal weighting means, excluding said center tap weighting means for producing at a first output port a signal which is a sum of tap-weighted signals; first signal combining means having a first input coupled to receive said sum of tap-weighted signals and a second input coupled to said center tap weighting means for combining applied signals in a first sense to produce output signals occupying a relatively high frequency portion of said contiguous frequency range; and second signal combining means having a first input coupled to receive said sum of tap-weighted signals and a second input coupled to said center tap weighting means for combining applied signals in a second sense to produce output signals occupying a relatively low frequency portion of said contiguous frequency range, wherein the frequency responses of said first and second signal combining means are completely transfer functions.

Claim 5

A digital filter, responsive to a comb filtered chrominance input signal for producing first and second output signals at outputs exhibiting complementary frequency response characteristics, comprising: a shift register coupled to receive an input signal and having a plurality of output taps including an intermediate output tap; means coupled to said plurality of taps excluding the intermediate output tap, and having an output, for weighting and combining signals developed at said plurality of taps; signal weighting means coupled to said intermediate output tap; first signal combining means coupled to said intermediate output tap signal weighting means and to said weighting and combining means, for combining applied signals in a first sense, and producing an output signal including a range of frequencies occupied by chrominance signal; and second signal combining means coupled to receive signals from said intermediate output tap signal weighting means and to said weighting and combining means, for combining applied signals in a second sense, and producing an output signal excluding said range of frequencies occupied by chrominance signal.

Claim 6

A digital filter, responsive to a comb filtered chrominance input signal for producing first and second output signals at outputs exhibiting complementary frequency response characteristics, comprising: a shift register coupled to receive an input signal and having a plurality of output taps including an intermediate output tap; means coupled to said plurality of taps excluding the intermediate output tap, and having an output, for weighting and combining signals developed at said plurality of taps; signal weighting means coupled to said intermediate output tap; first signal combining means coupled to said intermediate output tap signal weighting means and to said weighting and combining means, for combining applied signals in a first sense, and producing an output signal including a range of frequencies occupied by chrominance signal; and second signal combining means coupled to receive signals from said intermediate output tap signal weighting means and to said weighting and combining means, for combining applied signals in a second sense, and producing an output signal excluding said range of frequencies occupied by chrominance signal.

Claim 7

The arrangement of claim 2, wherein said plurality of output taps of said shift register is symmetrically located with respect to said intermediate output tap; and wherein said weighting and combining means includes a plurality of weighting function circuits coupled to ones of said plurality of output taps and exhibiting symmetrical weighting function values about said intermediate output tap, and an adder tree coupled to said weighting function circuits and having an output corresponding to the output of said weighting and combining means at which a tap-weighted signal is produced.

Claim 8

The arrangement of claim 3, wherein said first signal combining means comprises an additive signal combiner for additively combining signals produced at said output of said adder tree with tap-weighted signals derived from said intermediate tap; and said second signal combining means comprises a subtractive signal combiner for subtractively combining signals produced at said output of said adder tree with tap-weighted signals derived from said intermediate tap.

Claim 9

A digital filter, responsive to an input signal for producing first and second output signals at outputs exhibiting different response characteristics comprising: a source of input signal; a shift register including a plurality of serially coupled stages and having a plurality of adders coupled between ones of said stages, said adders having respective first input ports coupled respectively to immediately preceding shift register stages, having respective second input ports and having respective output ports respectively coupled to immediately succeeding register stages; said shift register having an input port and an output port at the firstmost and lastmost of said serially coupled stages respectively; respective means, responsive to said input signal, for applying weighting signals to respective second input ports of ones of said adders and said shift register input port; means, responsive to said input signal for producing signals at an output which are delayed by at least half the delay of said shift register; first signal combining means, coupled to said output of said shift register and to said signal delaying means, for combining signals applied thereto in a first sense to produce an output signal exhibiting a first amplitude versus frequency response characteristic; and second signal combining means, coupled to said output of said shift register and to said signal delaying means, for combining signals applied thereto in a second sense to produce a second output signal exhibiting a second amplitude versus frequency response characteristic.

Claim 10

A digital filter, responsive to an input signal for producing first and second output signals at outputs exhibiting different response characteristics comprising: a source of input signal; a shift register including a plurality of serially coupled stages and having a plurality of adders coupled between ones of said stages, said adders having respective first input ports coupled respectively to immediately preceding shift register stages, having respective second input ports and having respective output ports respectively coupled to immediately succeeding register stages; said shift register having an input port and an output port at the firstmost and lastmost of said serially coupled stages respectively; respective means, responsive to said input signal, for applying weighting signals to respective second input ports of ones of said adders and said shift register input port; means, responsive to said input signal for producing signals at an output which are delayed by at least half the delay of said shift register; first signal combining means, coupled to said output of said shift register and to said signal delaying means, for combining signals applied thereto in a first sense to produce an output signal exhibiting a first amplitude versus frequency response characteristic; and second signal combining means, coupled to said output of said shift register and to said signal delaying means, for combining signals applied thereto in a second sense to produce a second output signal exhibiting a second amplitude versus frequency response characteristic.

Claim 11

The arrangement of claim 5, wherein said weighted signal applying means comprises a plurality of weighting function circuits having symmetrical weighting function values with respect to an intermediate point of said shift register, and wherein said plurality of adders are symmetrically located about said intermediate point of said shift register.

Claim 12

The arrangement of claim 6, wherein said signal delaying means includes the series combination of a weighting function circuit and a second shift register having half the number of stages as said first-named shift register.

Claim 13

The arrangement of claim 7 wherein said first signal combining means comprises an additive signal combiner for additively combining signals produced by said signal delaying means and said first-named shift resister; and said second signal combining means comprises a subtractive signal combiner for subtractively combining signals produced by said signal delaying means and said first-named shift resister.

Claim 14

The arrangement of claims 4 or 8, wherein said subtractive signal combiner includes means for two's complementing one of said applied signals, and an adder.

Claim 15

The arrangement of claim 3 or 6 wherein said weighting function circuits comprise shift-and-add circuits.