Patent US3102816A successfully refreshed from Google Patents.
US4701422A
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US
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Method of adjusting threshold voltage subsequent to fabrication of transistor
Assignee: Conexant Systems LLC
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Filing: 1986-04-07
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Granted: 1987-10-20
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Expires: 2006-04-07
Abstract
Abstract A method of adjusting the threshold voltages of field effect transistors fabricated on a III-V compound semi-insulating wafer includes the steps of measuring the threshold voltages of the transistor, directing an ion beam at the wafer to selectively damage the channels of the transistors, thereby shifting the threshold voltages to an interim value, and annealing the wafer at a temperature and for a time sufficient to stabilize the threshold voltages at a predetermined optimum value determined by the intensity and duration of the ion beam implantation. The III-V compound semi-insulating wafer may be GaAs. The ion beam may be supplied as protons accelerated to approximately 320 KeV with a concentration of between approximately 10 11 and 10 13 protons/cm -2 . The wafer may be annealed at a temperature from approximately 100° C. to approximately 300° C. (for approximately one half hour at 300° C. The field effect transistors may be depletion mode or enhancement mode field effect transistors. In addition, the field effect transistors may initially be depletion mode field effect transistors, but the intensity and duration of the directed ion beam may be made sufficient to convert the transistors into enhancement mode transistors.
Inventors
- 👤 Kenneth R. Elliott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 03:25
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/206; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/50; H10D62/53; H10P30/208; Y; Y10; Y10S; Y10S148/00; Y10S148/084
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
106 words
A method of adjusting the threshold voltages of field effect transistors fabricated on a III-V compound semi-insulating wafer, comprising the steps of, subsequent to the fabrication of the transistors: measuring the threshold voltages of the transistors; directing an ion beam at the wafer to selectively damage the channels of the transistors, thereby shifting the threshold voltages to an interim value; and annealing the wafer at a temperature and for a time sufficient to stabilize the threshold voltages at a predetermined optimum value determined by the intensity and duration of the ion beam implanation, the annealing temperature being low enough to avoid damaging the previously fabricated transistors.
Claim 2
Independent Claim
106 words
A method of adjusting the threshold voltages of field effect transistors fabricated on a III-V compound semi-insulating wafer, comprising the steps of, subsequent to the fabrication of the transistors: measuring the threshold voltages of the transistors; directing an ion beam at the wafer to selectively damage the channels of the transistors, thereby shifting the threshold voltages to an interim value; and annealing the wafer at a temperature and for a time sufficient to stabilize the threshold voltages at a predetermined optimum value determined by the intensity and duration of the ion beam implanation, the annealing temperature being low enough to avoid damaging the previously fabricated transistors.
Claim 3
Dependent Claim
14 words
The method of claim 1, wherein the III-V compound semi-insulating wafer further comprises GaAs.
Claim 4
Dependent Claim
17 words
The method of claim 1, wherein the field effect transistors further comprise depletion mode field effect transistors.
Claim 5
Dependent Claim
17 words
The method of claim 1, wherein the field effect transistors further comprise enhancement mode field effect transistors.
Claim 6
Dependent Claim
38 words
The method of claim 1, wherein the field effect transistors initially comprise depletion mode field effect transistors, but wherein the intensity and duration of the directed ion beam are sufficient to convert the transistors into enhancement mode transistors.
Claim 7
Dependent Claim
32 words
The method of claim 2, wherein the ion beam further comprises protons accelerated to approximately 320 KeV with an integrated dose of between approximately 10 11 and 10 13 protons/cm -2 .
Claim 8
Dependent Claim
21 words
The method of claim 6, wherein the wafer is annealed at a temperature from approximately 100° C. to approximately 300° C.
Claim 9
Dependent Claim
175 words
An improved method of fabricating field effect transistors on a III-V compound semi-insulating wafer, of the type including the steps of depositing a first photolithographic mask on the wafer, defining the transistor channels with a first ion implanation, depositing a second photolithographic mask on the wafer, defining the transistor gates with a second ion implanation, annealing the wafer to activate the transistors, depositing a third photolithographic mask on the wafer, and depositing metallic contacts to the source, gate, and drain of each transistor, wherein the improvement comprises, subsequent to the step of depositing metallic contacts, the steps of: measuring the threshold voltages of the transistors; directing an ion beam at the wafer to selectively damage the channels of the transistors, thereby shifting the threshold voltages to an interim value; and annealing the wafer at a temperature and for a time sufficient to stabilize the threshold voltages at a predetermined optimum value determined by the intensity and duration of the ion beam implanation, the annealing temperature being low enough to avoid damaging the previously fabricated transistors.
Claim 10
Dependent Claim
175 words
An improved method of fabricating field effect transistors on a III-V compound semi-insulating wafer, of the type including the steps of depositing a first photolithographic mask on the wafer, defining the transistor channels with a first ion implanation, depositing a second photolithographic mask on the wafer, defining the transistor gates with a second ion implanation, annealing the wafer to activate the transistors, depositing a third photolithographic mask on the wafer, and depositing metallic contacts to the source, gate, and drain of each transistor, wherein the improvement comprises, subsequent to the step of depositing metallic contacts, the steps of: measuring the threshold voltages of the transistors; directing an ion beam at the wafer to selectively damage the channels of the transistors, thereby shifting the threshold voltages to an interim value; and annealing the wafer at a temperature and for a time sufficient to stabilize the threshold voltages at a predetermined optimum value determined by the intensity and duration of the ion beam implanation, the annealing temperature being low enough to avoid damaging the previously fabricated transistors.
Claim 11
Dependent Claim
14 words
The method of claim 8, wherein the III-V compound semi-insulating wafer further comprises GaAs.
Claim 12
Dependent Claim
17 words
The method of claim 8, wherein the field effect transistors further comprise depletion mode field effect transistors.
Claim 13
Dependent Claim
17 words
The method of claim 8, wherein the field effect transistors further comprise enhancement mode field effect transistors.
Claim 14
Dependent Claim
38 words
The method of claim 8, wherein the field effect transistors initially comprise depletion mode field effect transistors, but wherein the intensity and duration of the directed ion beam are sufficient to convert the transistors into enhancement mode transistors.
Claim 15
Independent Claim
105 words
A method of adjusting the threshold voltages of field effect transistors fabricated on a GaAs semi-insulating wafer, comprising the steps of, subsequent to the fabrication of the transistors: measuring the threshold voltages of the transistors; directing an ion beam at the wafer to selectively damage the channels of the transistors, thereby shifting the threshold voltages to an interim value; and annealing the wafer at a temperature and for a time sufficient to stabilize the threshold voltages at a predetermined optimum value determined by the intensity and duration of the ion beam implanation, the annealing temperature being low enough to avoid damaging the previously fabricated transistors.
Claim 16
Independent Claim
105 words
A method of adjusting the threshold voltages of field effect transistors fabricated on a GaAs semi-insulating wafer, comprising the steps of, subsequent to the fabrication of the transistors: measuring the threshold voltages of the transistors; directing an ion beam at the wafer to selectively damage the channels of the transistors, thereby shifting the threshold voltages to an interim value; and annealing the wafer at a temperature and for a time sufficient to stabilize the threshold voltages at a predetermined optimum value determined by the intensity and duration of the ion beam implanation, the annealing temperature being low enough to avoid damaging the previously fabricated transistors.
Claim 17
Dependent Claim
17 words
The method of claim 13, wherein the field effect transistors further comprise depletion mode field effect transistors.
Claim 18
Dependent Claim
17 words
The method of claim 13, wherein the field effect transistors further comprise enhancement mode field effect transistors.
Claim 19
Dependent Claim
38 words
The method of claim 13, wherein the field effect transistors initially comprise depletion mode field effect transistors, but wherein the intensity and duration of the directed ion beam are sufficient to convert the transistors into enhancement mode transistors.
References Cited (Backward Citations)
US4244097A
Cited
US4469528A
Cited
US4452646A
Cited
US4473939A
Cited
JPS59194431A
Cited
US4606113A
Cited
JPS6047428A
Cited
US4558509A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-19 | 1991-04-20 | 1991-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-19 | 1995-04-20 | 1995-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-19 | 1999-04-20 | 1999-10-20 | $7700.00 | Window Closed / Lapsed |