Patent US4700089A successfully refreshed from Google Patents.
US4700089A
Expired / Lapsed
US
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Delay circuit for gate-array LSI
Assignee: Fujitsu Ltd
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Filing: 1985-08-20
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Granted: 1987-10-13
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Expires: 2005-08-20
Abstract
Abstract A delay circuit for a gate-array LSI including at least one inverter having a plurality of P-channel transistors (Q 1p to Q 4p ) and a plurality of N-channel transistors (Q 1n to Q 4n ) connected in series. The P-channel/N-channel transistors are driven by an input potential (IN), and the common output of the innermost pair of P-channel/N-channel transistors generates an output.
Inventors
- 👤 Shigeru Fujii
- 👤 Masanori Oozeki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:22
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/133; H03K2005/00013; H03K2005/0015; H03K2005/00195; H03K2005/00215
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
217 words
A delay circuit comprising: an input terminal (IN); an intermediate terminal (C); an output terminal (OUT); first and second power supply means (V cc , GND); a first inverter (INVA) connected between said input terminal and said intermediate terminal, said first inverter comprising: a plurality of first P-channel transistors (Q 1p to Q 4p ) connected in series between said first power supply means and said intermediate terminal, said first P-channel transistors being driven by the potential at said input terminal; a plurality of first N-channel transistors (Q 1n to Q 4n ) connected in series between said intermediate terminal and said second power supply terminal, said first N-channel transistors being driven by the potential at said input terminal; and a second inverter (INVB) connected between said intermediate terminal and said output terminal, said second inverter comprising: a plurality of second P-channel transistors to (Q 1p ' to Q 4p ') connected in series between said first power supply means and said output terminal, said second P-channel transistors being driven by the potential at said intermediate terminal, and a plurality of second N-channel transistors (Q 1n ' to Q 4n ') connected in series between said output terminal and said second power supply terminal, said second N-channel transistors being driven by the potential at said intermediate terminal.
Claim 2
Dependent Claim
217 words
A delay circuit comprising: an input terminal (IN); an intermediate terminal (C); an output terminal (OUT); first and second power supply means (V cc , GND); a first inverter (INVA) connected between said input terminal and said intermediate terminal, said first inverter comprising: a plurality of first P-channel transistors (Q 1p to Q 4p ) connected in series between said first power supply means and said intermediate terminal, said first P-channel transistors being driven by the potential at said input terminal; a plurality of first N-channel transistors (Q 1n to Q 4n ) connected in series between said intermediate terminal and said second power supply terminal, said first N-channel transistors being driven by the potential at said input terminal; and a second inverter (INVB) connected between said intermediate terminal and said output terminal, said second inverter comprising: a plurality of second P-channel transistors to (Q 1p ' to Q 4p ') connected in series between said first power supply means and said output terminal, said second P-channel transistors being driven by the potential at said intermediate terminal, and a plurality of second N-channel transistors (Q 1n ' to Q 4n ') connected in series between said output terminal and said second power supply terminal, said second N-channel transistors being driven by the potential at said intermediate terminal.
Claim 3
Dependent Claim
58 words
A circuit as set forth in claim 1, further comprising: a third inverter (INVA') connected between said first and second inverters, said third inverter comprising a pair of P-channel/N-channel transistors connected in series, and a fourth inverter (INVB') connected to the output of said second inverter, said fourth inverter comprising a pair of P-channel/N-channel transistors connected in series.
Claim 4
Dependent Claim
99 words
A delay circuit comprising: an input terminal (IN); an output terminal (OUT); first and second power supply means (V cc , GND); and first and second inverters (INVA, INVB) connected in series between said input terminal and said output terminal, each of said first and second inverters having the same number of P-channel transistors and N-channel transistors connected in series between said first and second power supply terminals; the common outputs of some of the pairs of P-channel/N-channel transistors of said second inverter being fed back to the inputs of the pairs of P-channel/N-channel transistors of said first inverter.
Claim 5
Dependent Claim
99 words
A delay circuit comprising: an input terminal (IN); an output terminal (OUT); first and second power supply means (V cc , GND); and first and second inverters (INVA, INVB) connected in series between said input terminal and said output terminal, each of said first and second inverters having the same number of P-channel transistors and N-channel transistors connected in series between said first and second power supply terminals; the common outputs of some of the pairs of P-channel/N-channel transistors of said second inverter being fed back to the inputs of the pairs of P-channel/N-channel transistors of said first inverter.
Claim 6
Dependent Claim
153 words
A delay circuit comprising: an input terminal (IN); an output terminal (OUT); first and second power supply means (V cc , GND); and first and second inverters (INVA, INVB) each having the same number of P-channel transistors and N-channel transistors connected in series between said first and second power supply means; the outermost pair of P-channel/N-channel transistors of said first inverter being driven by the potential at said input terminal; the pairs of P-channel/N-channel transistors of said second inverter being sequentially driven from the outside to the inside by each common output of the pairs of P-channel/N-channel transistors of said first inverter; the pairs of P-channel/N-channel transistors of said first inverter, except for the outermost pair, being sequentially driven by each common output of the pairs of P-channel/N-channel transistors of said second inverter; the common output of the innermost pair of P-channel/N-channel transistors of said second inverter being connected to said output terminal.
Claim 7
Dependent Claim
153 words
A delay circuit comprising: an input terminal (IN); an output terminal (OUT); first and second power supply means (V cc , GND); and first and second inverters (INVA, INVB) each having the same number of P-channel transistors and N-channel transistors connected in series between said first and second power supply means; the outermost pair of P-channel/N-channel transistors of said first inverter being driven by the potential at said input terminal; the pairs of P-channel/N-channel transistors of said second inverter being sequentially driven from the outside to the inside by each common output of the pairs of P-channel/N-channel transistors of said first inverter; the pairs of P-channel/N-channel transistors of said first inverter, except for the outermost pair, being sequentially driven by each common output of the pairs of P-channel/N-channel transistors of said second inverter; the common output of the innermost pair of P-channel/N-channel transistors of said second inverter being connected to said output terminal.
Claim 8
Dependent Claim
170 words
A delay circuit comprising: an input terminal (IN); an output terminal (OUT); first and second power supply means (V cc , GND); and first and second inverters (INVA, INVB) each having the same number of P-channel transistors and N-channel transistors connected in series between said first and second power supply means; the outermost pair of P-channel/N-channel transistors of said first inverter being driven by the potential at said input terminal; the outermost pair of P-channel/N-channel transistors of said second inverter being driven by the common output of the outermost pair of P-channel/N-channel transistors of said first inverter; the inside pairs of P-channel/N-channel transistors of said first inverter being driven by the common output of the outermost pair of P-channel/N-channel transistors of said second inverter; the inside pairs of P-channel/N-channel transistors of said second inverter being driven by the common output of the innermost pair of P-channel/N-channel transistors of said first inverter; the output of the innermost pair of P-channel/N-channel transistors of said second inverter being connected to said output terminal.
Claim 9
Dependent Claim
170 words
A delay circuit comprising: an input terminal (IN); an output terminal (OUT); first and second power supply means (V cc , GND); and first and second inverters (INVA, INVB) each having the same number of P-channel transistors and N-channel transistors connected in series between said first and second power supply means; the outermost pair of P-channel/N-channel transistors of said first inverter being driven by the potential at said input terminal; the outermost pair of P-channel/N-channel transistors of said second inverter being driven by the common output of the outermost pair of P-channel/N-channel transistors of said first inverter; the inside pairs of P-channel/N-channel transistors of said first inverter being driven by the common output of the outermost pair of P-channel/N-channel transistors of said second inverter; the inside pairs of P-channel/N-channel transistors of said second inverter being driven by the common output of the innermost pair of P-channel/N-channel transistors of said first inverter; the output of the innermost pair of P-channel/N-channel transistors of said second inverter being connected to said output terminal.
Claim 10
Dependent Claim
170 words
A delay circuit comprising: an input terminal (IN); an output terminal (OUT); first and second power supply means (V cc , GND); and first and second inverters (INVA, INVB) each having the same number of P-channel transistors and N-channel transistors connected in series between said first and second power supply means; the outermost pair of P-channel/N-channel transistors of said first inverter being driven by the potential at said input terminal; the outermost pair of P-channel/N-channel transistors of said second inverter being driven by the common output of the outermost pair of P-channel/N-channel transistors of said first inverter; the inside pairs of P-channel/N-channel transistors of said first inverter being driven by the common output of the innermost pair of P-channel/N-channel transistors of said second inverter; the inside pairs of P-channel/N-channel transistors of said second inverter being driven by the common output of the innermost pair of P-channel/N-channel transistors of said first inverter; the output of the innermost pair of P-channel/N-channel transistors of said second inverter being connected to said output terminal.
Claim 11
Dependent Claim
170 words
A delay circuit comprising: an input terminal (IN); an output terminal (OUT); first and second power supply means (V cc , GND); and first and second inverters (INVA, INVB) each having the same number of P-channel transistors and N-channel transistors connected in series between said first and second power supply means; the outermost pair of P-channel/N-channel transistors of said first inverter being driven by the potential at said input terminal; the outermost pair of P-channel/N-channel transistors of said second inverter being driven by the common output of the outermost pair of P-channel/N-channel transistors of said first inverter; the inside pairs of P-channel/N-channel transistors of said first inverter being driven by the common output of the innermost pair of P-channel/N-channel transistors of said second inverter; the inside pairs of P-channel/N-channel transistors of said second inverter being driven by the common output of the innermost pair of P-channel/N-channel transistors of said first inverter; the output of the innermost pair of P-channel/N-channel transistors of said second inverter being connected to said output terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-12 | 1991-04-13 | 1991-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-12 | 1995-04-13 | 1995-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-12 | 1999-04-13 | 1999-10-13 | $7700.00 | Window Closed / Lapsed |