Write strobe generator for clock synchronized memory

Claim 2

A circuit for generating a plurality of output pulses, each in response to one of a plurality of input pulses and occurring at a predetermined period of time thereafter, comprising: first means for receiving said plurality of input pulses and generating therefrom a symmetrical pulse train having a reduced frequency; second means coupled to said first means for generating a trigger pulse of a first predetermined duration at every transition of said symmetrical pulse train, said second means including first delay means having a delay time corresponding to said first predetermined duration; third means coupled to said second means for delaying each of said trigger pulses; and switching means coupled to said second and third means for receiving therefrom said trigger pulses and the delayed trigger pulses and for generating therefrom said plurality of output pulses.

Claim 3

A circuit according to claim 1 wherein said second means comprises a level change detector which receives said symmetrical pulse train and issues in response thereto a pulse of said first predetermined duration whenever a level change in said symmetrical pulse train is detected.

Claim 4

A circuit according to claim 2 wherein said level change detector comprises: a first inverter having an input coupled to receive said symmetrical pulse train and having an output; first delay means having an input coupled to the output of said first inverter and having an output; second delay means having an input coupled to receive said symmetrical pulse train and having an output; a first P-channel field effect transistor having a drain adapted to be coupled to a first source of supply voltage, a gate coupled to the output of said first inverter and having a source; a second P-channel field effect transistor having a drain coupled to the source of said first P-channel field effect transistor, a gate coupled to the output of said first delay means, and having a source; a first N-channel field effect transistor having a drain coupled to the source of said second P-channel field effect transistor, a gate coupled to the output of said first delay means, and having a source; a second N-channel field effect transistor having a drain coupled to the source of said first N-channel field effect transistor, a gate coupled to receive said symmetrical pulse train, and a source adapted to be coupled to a second source of supply voltage; a third P-channel field effect transistor having a drain adapted to be coupled to said first source of supply voltage, a gate coupled to receive said symmetrical pulse drain, and having a source; a fourth P-channel field effect transistor having a drain coupled to the source of said third P-channel field effect transistor, a gate coupled to the output of said second delay means and having a source; a third N-channel field effect transistor having a drain coupled to the source of said fourth P-channel field effect transistor and to the source drain junction of said second P-channel field effect transistor and said first N-channel field effect transistor, a gate coupled to the output of said first inverter and a source coupled to the source-drain junction of said first and second N-channel field effect transistor; and a fourth N-channel field effect transistor having a drain coupled to the source of said third N-channel field effect transistor, a gate coupled to the output of said second delay means and a source adapted to be coupled to said second source of supply voltage, said trigger pulses appearing at the source-drain junction of said second P-channel field effect transistor and said first N-channel field effect transistor and at the source-drain junction of said fourth P-channel field effect transistor and said third N-channel field effect transistor.

Claim 5

Circuit according to claim 2 wherein said first means comprises a flip-flop for generating said pulse train having half the frequency of said input pulses.

Claim 6

A circuit according to claim 4 wherein said flip-flop is a delay flip-flop having its Q output coupled to its D input.

Claim 7

A circuit according to claim 4 wherein said trigger pulses are negative going pulses having a width corresponding to the delay imparted by said first delay means.

Claim 8

A circuit according to claim 4 wherein said switching means comprises an asynchronous flip-flop having a first input coupled to receive said trigger pulses and a second input coupled to receive the delayed trigger pulses.

Claim 9

An on-chip memory control circuit for use in a clock synchronized integrated circuit memory chip for generating a WRITE STROBE signal at a predetermined period of time after the occurance of an input clock signal comprising a train of clock pulses, comprising: first means for receiving said clock pulses and generating therefrom a symmetrical clock signal having a reduced frequency; second means coupled to said first means for generating a trigger pulse of a first predetermined duration at every transition of said symmetrical clock signals, said second means including first delay means having a delay time corresponding to said first predetermined duration; third means coupled to said second means for delaying each of said trigger pulses; and switching means coupled to said second and third means for receiving therefrom said trigger pulses and the delayed trigger pulses respectively and for generating therefrom said WRITE STROBE signal.

Claim 10

An on-chip memory control circuit for use in a clock synchronized integrated circuit memory chip for generating a WRITE STROBE signal at a predetermined period of time after the occurance of an input clock signal comprising a train of clock pulses, comprising: first means for receiving said clock pulses and generating therefrom a symmetrical clock signal having a reduced frequency; second means coupled to said first means for generating a trigger pulse of a first predetermined duration at every transition of said symmetrical clock signals, said second means including first delay means having a delay time corresponding to said first predetermined duration; third means coupled to said second means for delaying each of said trigger pulses; and switching means coupled to said second and third means for receiving therefrom said trigger pulses and the delayed trigger pulses respectively and for generating therefrom said WRITE STROBE signal.

Claim 11

A circuit according to claim 8 wherein said second means comprises a level change detector which issues a trigger pulse at every transition of said symmetrical clock signal.

Claim 12

A circuit according to claim 9 wherein said first means comprises a flip-flop for reducing the frequency of said clock signal by a factor of two.