Patent US4697108A successfully refreshed from Google Patents.
US4697108A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Complementary input circuit with nonlinear front end and partially coupled latch
Assignee: International Business Machines Corp
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Filing: 1986-05-09
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Granted: 1987-09-29
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Expires: 2006-05-09
Abstract
Abstract A complementary input circuit with a nonlinear front end is used to transfer the state of an external input to the internal signal lines of an intetraged circuit chip such as a dynamic or static RAM. The combination of a nonlinear front end and a "partially" cross-coupled complementary latch provide good level detection.
Inventors
- 👤 Barbara A. Chappell
- 👤 Stanley E. Schuster
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:59
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356113; H03K3/356017
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
318 words
An input circuit for transferring the state of an input external to an integrated circuit chip to the internal signal lines of the integrated circuit chip comprising: a nonlinear input circuit having an input terminal for receiving an external input and providing an output to a first node only when the external input exceeds a reference voltage plus a threshold voltage, said nonlinear input circuit including first and second complementary conductivity transistor devices connected in series between said input terminal and said first node, each of said first and second transistor devices having a control input terminal, the control input terminal of said first transistor device being connected to a control node for turning said first transistor device off after voltage transfer is complete and the control input terminal of said second transistor device being connected to a reference voltage source; and latch means including third and fourth complementary conductivity transistor devices connected in series between a common node and ground and fifth and sixth complementary conductivity transistor devices connected in series between said common node and ground, the common connections between said third and fourth transistor devices and between said fifth and sixth transistor devices being first and second output nodes, respectively, of said latch means, said first and second output nodes being connected to the internal signal lines of the integrated circuit chip, each of said third, fourth, fifth and sixth transistor devices having a control electrode, the control electrode of said third transistor device being connected to said second output node of said latch means which is the common connection between said first and sixth transistor devices, the control electrodes of said fifth and sixth transistor devices being connected to said first output node of said latch means which is the common connection between said third and fourth transistor devices, and the control electrode of said fourth transistor device being connected to said first node.
Claim 2
Dependent Claim
318 words
An input circuit for transferring the state of an input external to an integrated circuit chip to the internal signal lines of the integrated circuit chip comprising: a nonlinear input circuit having an input terminal for receiving an external input and providing an output to a first node only when the external input exceeds a reference voltage plus a threshold voltage, said nonlinear input circuit including first and second complementary conductivity transistor devices connected in series between said input terminal and said first node, each of said first and second transistor devices having a control input terminal, the control input terminal of said first transistor device being connected to a control node for turning said first transistor device off after voltage transfer is complete and the control input terminal of said second transistor device being connected to a reference voltage source; and latch means including third and fourth complementary conductivity transistor devices connected in series between a common node and ground and fifth and sixth complementary conductivity transistor devices connected in series between said common node and ground, the common connections between said third and fourth transistor devices and between said fifth and sixth transistor devices being first and second output nodes, respectively, of said latch means, said first and second output nodes being connected to the internal signal lines of the integrated circuit chip, each of said third, fourth, fifth and sixth transistor devices having a control electrode, the control electrode of said third transistor device being connected to said second output node of said latch means which is the common connection between said first and sixth transistor devices, the control electrodes of said fifth and sixth transistor devices being connected to said first output node of said latch means which is the common connection between said third and fourth transistor devices, and the control electrode of said fourth transistor device being connected to said first node.
Claim 3
Dependent Claim
76 words
The input circuit recited in claim 18 further comprising: a seventh transistor device connected between said common node and a source of voltage, said seventh transistor device hvaing a control electrode connected to a precharge voltage source; and eighth and ninth transistor devices of complementary conductivity to said seventh transistor device respectively connected in series between said output nodes and ground, said eighth and ninth transistor devices having control electrodes connected to said precharge voltage source.
Claim 4
Dependent Claim
85 words
The input circuit recited in claim 2 further comprising: first and second inverter/driver means respectively connected to said output nodes of said latch means to provide first and second internal outputs; a tenth transistor device connected to said first node and said source of voltage, said tenth transistor device having a control electrode connected to said first inverter/driver means; and switching circuit means connected to said first and second internal outputs for generating a control voltage for said control node of said nonlinear input circuit.
Claim 5
Dependent Claim
63 words
The input circuit recited in claim 3 wherein said nonlinear input circuit further includes an inverter connected to the common connection between said first and second transistor devices and an eleventh transistor device connected in series between said first node and ground, said inverter having an output and said eleventh transistor device having a control electrode connected to the output of said inverter.
Claim 6
Dependent Claim
43 words
The input circuit recited in claim 4 further comprising a twelth transistor device connected in series between the common connection of said first and second transistor devices and ground, said twelth transistor device having a control electrode connected to said second internal output.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-28 | 1991-03-30 | 1991-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-28 | 1995-03-30 | 1995-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-28 | 1999-03-30 | 1999-09-29 | $7700.00 | Window Closed / Lapsed |