US4489284A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Operational amplifier circuit for NMOS chip
Assignee: AD TECHNOLOGIES LLC
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Filing: 1983-01-03
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Granted: 1984-12-18
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Expires: 2003-01-03
Abstract
Abstract An operational amplifier circuit for use in high density L.S.I. chips incorporates four solid state silicon devices in a flip-flop-like configuration including a source follower function on the input side of the circuit while a depletion transistor provides for positive feedback and prohibits the circuit from latching thereby the circuit is locked to operate in a transition zone between switching states, providing a linear high gain function which can be operated as an amplifier.
Inventors
- 👤 Albert J. Charpentier
- 👤 James W. Redfield
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:20
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/34; H03F3/343; H03F3/345
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
140 words
An operational amplifier circuit for high density LSI solid state circuits, having an input and output terminals, comprising: first silicon circuit means for achieving a relatively high virtual ground level; second silicon circuit means for amplifying said first silicon circuit means output, said second silicon circuit means being connected to said first silicon circuit means and to said output terminal; third silicon circuit means for maintaining said second silicon circuit means output high, said third silicon circuit means being connected thereto; and fourth silicon circuit means being connected to said second silicon circuit means output and said first silicon circuit means output for providing a positive feedback path and for continuously conducting and thereby depleting the signal on said first silicon circuit output and prohibiting a latched state of said second and third silicon circuit means at said output terminal.
Claim 2
Dependent Claim
140 words
An operational amplifier circuit for high density LSI solid state circuits, having an input and output terminals, comprising: first silicon circuit means for achieving a relatively high virtual ground level; second silicon circuit means for amplifying said first silicon circuit means output, said second silicon circuit means being connected to said first silicon circuit means and to said output terminal; third silicon circuit means for maintaining said second silicon circuit means output high, said third silicon circuit means being connected thereto; and fourth silicon circuit means being connected to said second silicon circuit means output and said first silicon circuit means output for providing a positive feedback path and for continuously conducting and thereby depleting the signal on said first silicon circuit output and prohibiting a latched state of said second and third silicon circuit means at said output terminal.
Claim 3
Dependent Claim
19 words
The circuit of claim 1 wherein said first and third silicon circuit means are paired in signal enhancement connection.
Claim 4
Dependent Claim
17 words
The circuit of claim 2 wherein said second silicon circuit means provides loading for said amplifier circuit.
Claim 5
Dependent Claim
16 words
The circuit of claim 3 wherein said third silicon circuit means includes a depletion type device.
Claim 6
Dependent Claim
52 words
The circuit of claim 4 wherein said first, second and fourth silicon circuit means comprise first, second and third silicon junction field effect transistors, respectively, each having gate, supply and drain pins, and wherein said third silicon circuit means comprises a depletion type field effect transistor, having gate supply and drain pins.
Claim 7
Dependent Claim
146 words
The circuit of claim 5 wherein the gate pin of said first junction field effect transistor is connected to the input terminal of said circuit; wherein the gate pin of said third junction field effect transistor is connected to the drain pin of said first junction field effect transistor; wherein the supply pin of said first and second junction field effect transistors is each connected to a voltage supply; and wherein the gate pin of said second junction field effect transistor is also connected to said voltage supply; wherein the drain pin of said second junction field effect transistor is connected in common to the output terminal of said circuit and to the gate pin of said depletion type field effect transistor; and wherein the drain pin of said depletion type field effect transistor and said third junction field effect transistor are each connected to ground.
References Cited (Backward Citations)
US4321491A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-18 | 1988-06-18 | 1988-12-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-18 | 1992-06-18 | 1992-12-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-18 | 1996-06-18 | 1996-12-18 | $7700.00 | Window Closed / Lapsed |