US4689505A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed bootstrapped CMOS driver
Assignee: Microelectronics and Computer Technology Corp
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Filing: 1986-11-13
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Granted: 1987-08-25
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Expires: 2006-11-13
Abstract
Abstract A bootstrapped CMOS driver circuit capable of driving large capacitance loads with small internal delays. Higher driving capability is achieved by using only n-channel transistors at the output and overdriving the transistors during the transitions. A total internal delay of less than one nanosecond for a driver may be provided with 100 ohms compatible output impedance.
Inventors
- 👤 Uttam S. Ghoshal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:53
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01714
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
150 words
A high speed CMOS driver circuit comprising, a plurality of transistors having source, gate and drain nodes, the gate nodes of a first, second, third, fifth and sixth transistor coupled to an input, the drain nodes of the fifth transistor, the sixth transistor and a fourth transistor being connected to a drain supply voltage, the source nodes of the first and second transistors being connected to ground, a capacitor one side of which is connected to the source node of the fifth transistor and the drain node of the third transistor and the other side connected to an output, the source node of the fourth transistor and the drain node of the second transistor connected to the output, the source node of the third transistor and the drain node of the first transistor and the gate node of the fourth transistor connected to the source node of the sixth transistor.
Claim 2
Dependent Claim
150 words
A high speed CMOS driver circuit comprising, a plurality of transistors having source, gate and drain nodes, the gate nodes of a first, second, third, fifth and sixth transistor coupled to an input, the drain nodes of the fifth transistor, the sixth transistor and a fourth transistor being connected to a drain supply voltage, the source nodes of the first and second transistors being connected to ground, a capacitor one side of which is connected to the source node of the fifth transistor and the drain node of the third transistor and the other side connected to an output, the source node of the fourth transistor and the drain node of the second transistor connected to the output, the source node of the third transistor and the drain node of the first transistor and the gate node of the fourth transistor connected to the source node of the sixth transistor.
Claim 3
Dependent Claim
14 words
The circuit of claim 1 wherein, the second and fourth transistors are n-channel transistors.
Claim 4
Dependent Claim
22 words
The circuit of claim 2 wherein the first and third transistors are n-channel transistors and the fifth transistor is a p-channel transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-24 | 1991-02-23 | 1991-08-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-24 | 1995-02-23 | 1995-08-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-24 | 1999-02-23 | 1999-08-25 | $7700.00 | Window Closed / Lapsed |