Patent US4423794A successfully refreshed from Google Patents.
US4408136A
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US
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MOS Bootstrapped buffer for voltage level conversion with fast output rise time
Assignee: STMicroelectronics lnc USA
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Filing: 1981-12-07
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Granted: 1983-10-04
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Expires: 2001-12-07
Abstract
Abstract A buffer circuit (10) receives a TTL input signal at an input node (12) and produces an MOS logic signal at an output node (38). A capacitor (22) is precharged by a precharge signal (PC) to a high voltage state and a control node (32) is precharged to a high voltage state. An input transistor (14) receives a reference voltage which is a function of the levels of the TTL input. When the TTL input is high the transistor (14) is nonconductive thereby maintaining the charge at the control node (32) to render conductive a pull-down transistor (36) which drives the output signal at the output node (38) to a low state. When the TTL input signal goes to a low voltage state the input transistor (14) is rendered conductive by discharging a terminal of the capacitor (22). A second terminal of the capacitor (22) is driven to a lower voltage state to render conductive a discharge transistor (30) which connects the control node (32) to the node ( 24) connected to capacitor (22). This serves to discharge the control node (32) thereby turning off the pull-down transistor (36) and permitting a pull-up transistor (40) to drive the output node (38) to a high voltage state. The buffer circuit (10) functions as an inverter and provides a rapid transition of the output signal in response to a transition of the input signal.
Inventors
- 👤 Howard C. Kirsch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:06
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/01855
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
129 words
A buffer circuit, comprising: a capacitor; means for precharging said capacitor to a first state; input transistor means connected to receive an input signal for driving said capacitor from said first state to a second state when said input signal transistions from a first voltage level to a second voltage level; a control node; means for precharging said control node; means connected to said capacitor and said control node for discharging said control node when said capacitor is driven from said first state to said second state; and output transistor means connected to said control node for driving an output node to a third voltage level when said control node is precharged and for driving said output node to a fourth voltage level when said control node is discharged.
Claim 2
Dependent Claim
129 words
A buffer circuit, comprising: a capacitor; means for precharging said capacitor to a first state; input transistor means connected to receive an input signal for driving said capacitor from said first state to a second state when said input signal transistions from a first voltage level to a second voltage level; a control node; means for precharging said control node; means connected to said capacitor and said control node for discharging said control node when said capacitor is driven from said first state to said second state; and output transistor means connected to said control node for driving an output node to a third voltage level when said control node is precharged and for driving said output node to a fourth voltage level when said control node is discharged.
Claim 3
Dependent Claim
82 words
The buffer circuit recited in claim 1 wherein said input transistor means comprises means for generating a reference voltage and a transistor having the gate terminal thereof connected to receive said reference voltage, the drain terminal thereof connected to said capacitor and the source terminal thereof connected to receive said input signal wherein said transistor is nonconductive when said input signal is at said first voltage level and said transistor is conductive when said input signal is at said second voltage level.
Claim 4
Dependent Claim
67 words
The buffer circuit recited in claim 1 wherein said means for discharging comprises a transistor having the gate terminal thereof connected to a common node and the source and drain terminals thereof connected between said capacitor and said control node wherein said transistor is rendered conductive when said capacitor is driven from said first state to said second state thereby discharging said control node through said transistor.
Claim 5
Dependent Claim
127 words
The buffer circuit recited in claim 1 wherein said output transistor means comprises: a first transistor having the gate terminal thereof connected to said control node, the drain terminal thereof connected to said output node and the source terminal thereof connected to a common node; a second transistor having the drain terminal thereof connected to a power terminal and the source terminal thereof connected to said output node; a third transistor having the gate terminal thereof connected to the gate terminal of said second transistor and the drain and source terminals thereof connected to said output node; and a fourth transistor having the gate and drain terminals thereof connected to said power terminal and the source terminal thereof connected to the gate terminal of said second transistor.
Claim 6
Dependent Claim
191 words
A buffer circuit comprising: an input transistor having the gate terminal thereof connected to receive a reference voltage, the source terminal thereof connected to receive an input signal having first and second voltage levels wherein said input transistor is nonconductive when the input signal is at said first voltage level and said input transistor is conductive when said input signal is at said second voltage level, the drain terminal thereof connected to a first node; a capacitor having the terminals thereof connected between said first node and a second node; a discharge transistor having the gate terminal thereof connected to a first power terminal and the source and drain terminals thereof connected between said second node and a third node; a pull down transistor having the gate terminal thereof connected to said third node and the source and drain terminals thereof connected between said first power terminal and an output node; pull up transistor means connected to said output node and to a second power terminal; and means for precharging said first and third nodes to a first voltage state and for precharging said second node to a second voltage state.
Claim 7
Dependent Claim
191 words
A buffer circuit comprising: an input transistor having the gate terminal thereof connected to receive a reference voltage, the source terminal thereof connected to receive an input signal having first and second voltage levels wherein said input transistor is nonconductive when the input signal is at said first voltage level and said input transistor is conductive when said input signal is at said second voltage level, the drain terminal thereof connected to a first node; a capacitor having the terminals thereof connected between said first node and a second node; a discharge transistor having the gate terminal thereof connected to a first power terminal and the source and drain terminals thereof connected between said second node and a third node; a pull down transistor having the gate terminal thereof connected to said third node and the source and drain terminals thereof connected between said first power terminal and an output node; pull up transistor means connected to said output node and to a second power terminal; and means for precharging said first and third nodes to a first voltage state and for precharging said second node to a second voltage state.
Claim 8
Dependent Claim
22 words
The buffer circuit recited in claim 5 wherein said first and second voltage levels are produced by a transistor-transistor logic (TTL) circuit.
Claim 9
Independent Claim
109 words
A method for voltage level conversion, comprising the steps of: precharging a capacitor; precharging a control node; discharging a first terminal of said capacitor in response to an input signal transitioning from a first voltage state to a second voltage state thereby driving a second terminal of said capacitor to a lower voltage state; discharging said control node in response to said second terminal of said capacitor being driven to said lower voltage state; driving an output node to a third voltage state in response to said control node being precharged; and driving said output node to a fourth voltage state in response to said control node being discharged.
Claim 10
Independent Claim
109 words
A method for voltage level conversion, comprising the steps of: precharging a capacitor; precharging a control node; discharging a first terminal of said capacitor in response to an input signal transitioning from a first voltage state to a second voltage state thereby driving a second terminal of said capacitor to a lower voltage state; discharging said control node in response to said second terminal of said capacitor being driven to said lower voltage state; driving an output node to a third voltage state in response to said control node being precharged; and driving said output node to a fourth voltage state in response to said control node being discharged.
Claim 11
Dependent Claim
66 words
The method recited in claim 7 wherein the step of discharging said capacitor comprises driving an input transistor connected to an input node, which receives said input signal and is connected to said first terminal, to a conductive state when said input signal transitions from said first voltage state to said second voltage state thereby discharging said capacitor through said first terminal to said input node.
Claim 12
Dependent Claim
46 words
The method recited in claim 7 wherein the step of discharging said control node comprises connecting said control node to the second terminal of said capacitor when said second terminal is driven to said lower voltage state to discharge said control node to said second terminal.
Claim 13
Dependent Claim
23 words
The method recited in claim 7 including the step of capacitively bootstrapping the driving of said output node to said third voltage state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-03 | 1987-04-04 | 1987-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-03 | 1991-04-04 | 1991-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-03 | 1995-04-04 | 1995-10-04 | $7700.00 | Window Closed / Lapsed |