US3859545A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low power dynamic control circuitry
Assignee: AT&T Inc
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Filing: 1973-12-10
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Granted: 1975-01-07
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Expires: 1993-12-10
Abstract
Abstract Improved low-power dynamic control circuits made up of MOS transistors are utilized as part of a dynamic memory system in order to improve the operating margins of the memory system.
Inventors
- 👤 Donald Gordon Clemons
- 👤 Paul Robert Schroeder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:01
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/023; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/405; G11C11/4063; G11C11/407; G11C11/4076
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
300 words
A circuit comprising: a first circuit means comprising a control port, a first port, and a second port; the first circuit means being adapted to selectively appear as an essentially open or short circuit; a second circuit means comprising a control port, a first port, and a second port; the second circuit means being adapted to selectively appear as an essentially open or short circuit; the second port of the first means being coupled to the first port of the second means; a first capacitive means, the first capacitive means being coupled between the first port and the control port of the second means; a third circuit means comprising a control port, a first port and a second port; the second port of the third circuit means being coupled to the control port of the second means, said third circuit means being adapted to selectively isolate or couple the first port of the third means to the control port of the second means; fourth circuit means, including second capacitive means, coupled to the first port and the control port of the third means for selectively controlling when the third circuit means isolates or couples the first port of the third circuit means to the control port of the second circuit means; the control port of the first circuit means being adapted to serve as an input port; the first port of the second circuit means being adapted to serve as an output port; the first port of the third circuit means being adapted to serve as an input port; an input port being coupled to the fourth circuit means; and the first port of the first circuit means, the second port of the second circuit means, and the fourth circuit means being adapted to be coupled to power supply means.
Claim 2
Dependent Claim
300 words
A circuit comprising: a first circuit means comprising a control port, a first port, and a second port; the first circuit means being adapted to selectively appear as an essentially open or short circuit; a second circuit means comprising a control port, a first port, and a second port; the second circuit means being adapted to selectively appear as an essentially open or short circuit; the second port of the first means being coupled to the first port of the second means; a first capacitive means, the first capacitive means being coupled between the first port and the control port of the second means; a third circuit means comprising a control port, a first port and a second port; the second port of the third circuit means being coupled to the control port of the second means, said third circuit means being adapted to selectively isolate or couple the first port of the third means to the control port of the second means; fourth circuit means, including second capacitive means, coupled to the first port and the control port of the third means for selectively controlling when the third circuit means isolates or couples the first port of the third circuit means to the control port of the second circuit means; the control port of the first circuit means being adapted to serve as an input port; the first port of the second circuit means being adapted to serve as an output port; the first port of the third circuit means being adapted to serve as an input port; an input port being coupled to the fourth circuit means; and the first port of the first circuit means, the second port of the second circuit means, and the fourth circuit means being adapted to be coupled to power supply means.
Claim 3
Dependent Claim
141 words
The apparatus of claim 1 wherein: the first, second and third circuit means are first, second and third field effect transistors, respectively; the first capacitive means comprises a fourth field effect transistor in which the drain and source of which are coupled together; the fourth circuit means comprises fifth, sixth and seventh field effect transistors, the drain and source of the fifth transistor being coupled together and being coupled to the source of the third transistor, the source of the sixth transistor being coupled to the gate of the third transistor, the source of the seventh transistor being coupled to the gates of the fifth and sixth transistors; the gate of the seventh transistor being adapted to serve as an input port; and the drains of the sixth and seventh transistors being adapted to be coupled to a power supply means.
Claim 4
Dependent Claim
76 words
The apparatus of claim 2 further comprising: eighth and ninth field effect transistors; a third capacitive means coupled between the source and gate of the third transistor; the drain of the eighth transistor being coupled to the gate of the third transistor; the drain of the ninth transistor being coupled to the source of the seventh transistor; and the sources of the eighth and ninth transistors being adapted to be coupled to a power supply means.
Claim 5
Dependent Claim
221 words
The apparatus of claim 3 further comprising: tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth and sixteenth field effect transistors; the drain of the tenth transistor being coupled to the source of the eleventh transistor and the gate of the first transistor; the source and drain of the twelfth transistor being coupled respectively to the source and drain of the first transistor, respectively; the gate of the twelfth transistor being coupled to the gate of the fourteenth transistor; the sources of the thirteenth and fourteenth transistors being coupled together and the drains of the thirteenth and fourteenth transistors being coupled together and being coupled to the gate of the second transistor; the gates of the thirteenth, fifteenth and sixteenth transistors being coupled together; the drain of the fifteenth transistor being coupled to the gate of the third transistor; the drain of the sixteenth transistor being coupled to the source of the seventh transistor; the gates of the tenth, twelfth, and sixteenth transistors all being adapted to serve as input ports, the tenth and eleventh transistors serving as buffers between any input signals applied thereto and the input port of the first transistor; and the sources of the tenth, twelfth, thirteenth, fourteenth, fifteenth and sixteenth transistors and the drain of the eleventh transistor all being adapted to be coupled to a power supply means.
Claim 6
Dependent Claim
293 words
A generator circuit comprising: sixteen transistors, T1-T16, each of the transistors comprising a first terminal, a second terminal and a control terminal; the second terminal of T1 being coupled to the first terminal of T2 and to the control terminal of T3; the first terminals of T3 and T4 being coupled together; the second terminals of T3 and T4 being coupled together and being coupled to the first and second terminals of T5, the first terminal of T6 and the control terminals of T7 and T8; the first terminals of T9 and T10 being coupled together, the second terminals of T9 and T10 being coupled together and being coupled to the control terminals of T5 and T6 and the second terminal of T11; the control terminal of T4 being coupled to the control terminal of T9; the control terminal of T11 being coupled to the first terminal of T12 and to the second terminals of T13 and T7; the control terminal of T13 being coupled to the control terminals of T14 and T10; the second terminal of T14 being coupled to the second terminal of T8, the first terminal of T15 and the control terminals of T12 and T16; the control terminals of T2 and T15 being coupled together; the first terminal of T11 being coupled to the first and second terminals of T16; the control terminals of T1, T2, T4, T14 and the first terminal of T11 all being adapted to serve as input terminals; the first terminal of T6 being adapted to serve as an output terminal; the first terminals of T1, T3, T4, T7, T8, T9, T10, T13 and T14 and the second terminals of T2, T6, T12 and T15 all being adapted to be coupled to power supply means.
Claim 7
Dependent Claim
293 words
A generator circuit comprising: sixteen transistors, T1-T16, each of the transistors comprising a first terminal, a second terminal and a control terminal; the second terminal of T1 being coupled to the first terminal of T2 and to the control terminal of T3; the first terminals of T3 and T4 being coupled together; the second terminals of T3 and T4 being coupled together and being coupled to the first and second terminals of T5, the first terminal of T6 and the control terminals of T7 and T8; the first terminals of T9 and T10 being coupled together, the second terminals of T9 and T10 being coupled together and being coupled to the control terminals of T5 and T6 and the second terminal of T11; the control terminal of T4 being coupled to the control terminal of T9; the control terminal of T11 being coupled to the first terminal of T12 and to the second terminals of T13 and T7; the control terminal of T13 being coupled to the control terminals of T14 and T10; the second terminal of T14 being coupled to the second terminal of T8, the first terminal of T15 and the control terminals of T12 and T16; the control terminals of T2 and T15 being coupled together; the first terminal of T11 being coupled to the first and second terminals of T16; the control terminals of T1, T2, T4, T14 and the first terminal of T11 all being adapted to serve as input terminals; the first terminal of T6 being adapted to serve as an output terminal; the first terminals of T1, T3, T4, T7, T8, T9, T10, T13 and T14 and the second terminals of T2, T6, T12 and T15 all being adapted to be coupled to power supply means.
Claim 8
Dependent Claim
12 words
The apparatus of claim 5 wherein the transistors are field effect-type transistors.
Claim 9
Dependent Claim
187 words
A generator circuit comprising: nine transistors, T1-T9, each of the transistors comprising a first terminal, a second terminal and a control terminal; the second terminal of T1 being coupled to the first and second terminals of T2, the first terminal of T3, and the control terminals of T4 and T5; the control terminal of T2 being coupled to the control terminal of T3 and the second terminal of T6; the control terminal of T6 being coupled to the first terminal of T7 and the second terminal of T4; the second terminal of T5 being coupled to the first terminal of T8 and to the control terminals of T7 ad T9; the first terminal of T6 being coupled to the first and second terminals of T9; the control terminals of T1 and T8 and the first terminal of T6 all being adapted to serve as input terminals; the first terminal of T3 being adapted to serve as an output terminal; and the first terminals of T1, T4 and T5 and the second terminals of T3, T7 and T8 all being adapted to be coupled to power supply means.
Claim 10
Dependent Claim
187 words
A generator circuit comprising: nine transistors, T1-T9, each of the transistors comprising a first terminal, a second terminal and a control terminal; the second terminal of T1 being coupled to the first and second terminals of T2, the first terminal of T3, and the control terminals of T4 and T5; the control terminal of T2 being coupled to the control terminal of T3 and the second terminal of T6; the control terminal of T6 being coupled to the first terminal of T7 and the second terminal of T4; the second terminal of T5 being coupled to the first terminal of T8 and to the control terminals of T7 ad T9; the first terminal of T6 being coupled to the first and second terminals of T9; the control terminals of T1 and T8 and the first terminal of T6 all being adapted to serve as input terminals; the first terminal of T3 being adapted to serve as an output terminal; and the first terminals of T1, T4 and T5 and the second terminals of T3, T7 and T8 all being adapted to be coupled to power supply means.
Claim 11
Dependent Claim
12 words
The apparatus of claim 7 wherein the transistors are field effect-type transistors.
Claim 12
Dependent Claim
167 words
A circuit comprising: seven transistors, T1-T7, each of the transistors comprising a first terminal, a second terminal and a control terminal; the second terminal of T1 being coupled to the first and seconD terminals of T2, and the first terminal of T3; the control terminal of T2 being coupled to the control terminal of T3 and the second terminal of T4; the control terminal of T4 being coupled to the first terminal of T6; the first terminal of T4 being coupled to the first and second terminals of T5; the control terminal of T5 being coupled to the control terminal of T6 and the first terminal of T7; the control terminal of T1 and T7 and the first terminal of T4 all being adapted to serve as input terminals; the first terminal of T3 being adapted to serve as an output terminal; and the first terminal of T1 and the second terminals of T3, T6, and T7 all being adapted to be coupled to power supply means.
Claim 13
Dependent Claim
167 words
A circuit comprising: seven transistors, T1-T7, each of the transistors comprising a first terminal, a second terminal and a control terminal; the second terminal of T1 being coupled to the first and seconD terminals of T2, and the first terminal of T3; the control terminal of T2 being coupled to the control terminal of T3 and the second terminal of T4; the control terminal of T4 being coupled to the first terminal of T6; the first terminal of T4 being coupled to the first and second terminals of T5; the control terminal of T5 being coupled to the control terminal of T6 and the first terminal of T7; the control terminal of T1 and T7 and the first terminal of T4 all being adapted to serve as input terminals; the first terminal of T3 being adapted to serve as an output terminal; and the first terminal of T1 and the second terminals of T3, T6, and T7 all being adapted to be coupled to power supply means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-01-06 | 1978-07-08 | 1979-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-01-06 | 1982-07-08 | 1983-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-01-06 | 1986-07-08 | 1987-01-07 | $7700.00 | Window Closed / Lapsed |