Delay stage for a clock generator

Claim 2

A delay stage which receives an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals, comprising: Schmitt trigger means connected between the first and second power terminals and to the input terminal for receiving the input signal and for generating a detection signal upon detecting a predetermined level of the input signal, wherein said Schmitt trigger means comprises; first, second and third transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming a first node between said first and second transistors and a second node between said second and third transistors, said gate terminals of said second and third transistors being connected to the input terminal; a fourth transistor having drain and source terminals connected between the first power terminal and said second node and a gate terminal thereof connected to said first node; and buffer means connected between the first power terminal and the Schmitt trigger means for receiving said detection signal and for generating the output signal at the output terminal without capacitively loading said Schmitt trigger means; wherein said buffer means comprises fifth and sixth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and said second node and forming a third node therebetween, said gate terminal of said fifth transistor connected to said first node, and said third node forming the output terminal and said gate terminal of said sixth transistor being connected to the input terminal.

Claim 3

A delay stage which receives an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals, comprising: first, second and third transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming a first node between said first and second transistors and a second node between said second and third transistors; a fourth transistor having drain, source and gate terminals connected between the first power terminal and said second node, said gate terminal thereof connected to said first node; fifth and sixth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and said second node, and forming a third node therebetween, said gate terminal of said fifth transistor connected to said first node, and said third node forming the output terminal; and said gate terminal of said second transistor, said gate terminal of said third transistor and said gate terminal of said sixth transistor being connected to the input terminal.

Claim 4

A delay stage which receives an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals, comprising: first, second and third transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming a first node between said first and second transistors and a second node between said second and third transistors; a fourth transistor having drain, source and gate terminals connected between the first power terminal and said second node, said gate terminal thereof connected to said first node; fifth and sixth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and said second node, and forming a third node therebetween, said gate terminal of said fifth transistor connected to said first node, and said third node forming the output terminal; and said gate terminal of said second transistor, said gate terminal of said third transistor and said gate terminal of said sixth transistor being connected to the input terminal.

Claim 5

The delay stage of claim 2 wherein said first transistor comprises a depletion type MOSFET.

Claim 6

The delay stage of claim 2 wherein said first transistor comprises a saturated enhancement type MOSFET, said gate terminal thereof being connected to the first power terminal.

Claim 7

The delay stage of claim 2 wherein said second, third, fourth and sixth transistors comprise enhancement type MOSFETs.

Claim 8

The delay stage of claim 2 wherein said fifth transistor comprises a MOSFET having a threshold voltage of approximately zero volts.

Claim 9

The delay stage of claim 2 wherein said first, second, third and fourth transistors comprise a Schmitt trigger stage and said fifth and sixth transistors comprise a push-pull inverter stage to prevent capacitive loading of said Schmitt trigger stage.

Claim 10

A delay stage which receives an input signal at an input terminal and is powered through first and second power terminals, comprising: a first transistor having drain, source and gate terminals, the drain terminal thereof connected to the first power terminal; a second transistor having drain, source and gate terminals, said drain terminal thereof connected to said source and gate terminals of said first transistor thereby forming a first node, said gate terminal thereof connected to the input terminal; a third transistor having drain, source and gate terminals, said drain terminal thereof connected to said source terminal of said second transistor thereby forming a second node, said gate terminal thereof connected to the input terminal, and said source terminal thereof connected to the second power terminal; a fourth transistor having drain, source and gate terminals, said drain terminal thereof connected to the first power terminal, said gate terminal thereof connected to said first node, and said source terminal thereof connected to said second node; a fifth transistor having drain, source and gate terminals, said drain terminal thereof connected to the first power terminal, and said gate terminal thereof connected to said first node; and a sixth transistor having drain, source and gate terminals, said drain terminal thereof connected to said source terminal of said fifth transistor, said gate terminal thereof connected to the input terminal, and said source terminal thereof connected to said second node.

Claim 11

A delay stage which receives an input signal at an input terminal and is powered through first and second power terminals, comprising: a first transistor having drain, source and gate terminals, the drain terminal thereof connected to the first power terminal; a second transistor having drain, source and gate terminals, said drain terminal thereof connected to said source and gate terminals of said first transistor thereby forming a first node, said gate terminal thereof connected to the input terminal; a third transistor having drain, source and gate terminals, said drain terminal thereof connected to said source terminal of said second transistor thereby forming a second node, said gate terminal thereof connected to the input terminal, and said source terminal thereof connected to the second power terminal; a fourth transistor having drain, source and gate terminals, said drain terminal thereof connected to the first power terminal, said gate terminal thereof connected to said first node, and said source terminal thereof connected to said second node; a fifth transistor having drain, source and gate terminals, said drain terminal thereof connected to the first power terminal, and said gate terminal thereof connected to said first node; and a sixth transistor having drain, source and gate terminals, said drain terminal thereof connected to said source terminal of said fifth transistor, said gate terminal thereof connected to the input terminal, and said source terminal thereof connected to said second node.

Claim 12

The delay stage of claim 8 wherein said first transistor comprises a depletion type MOSFET.

Claim 13

The delay stage of claim 8 wherein said first transistor comprises a saturated enhancement type MOSFET, said gate terminal thereof being connected to the first power terminal.

Claim 14

The delay stage of claim 8 wherein said second, third, fourth and sixth transistors comprise enhancement type MOSFETs.

Claim 15

The delay stage of claim 8 wherein said fifth transistor comprises a MOSFET having a threshold voltage of approximately zero volts.

Claim 16

The delay stage of claim 8 wherein said first, second, third and fourth transistors comprise a Schmitt trigger stage and said fifth and sixth transistors comprise a push-pull inverter stage to prevent capacitive loading of said Schmitt trigger stage.

Claim 17

A clock generator circuit for producing clocking signals wherein the clock generator circuit receives an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals, comprising: Schmitt trigger means connected between the first and second power terminals and to the input terminal for receiving the input signal and for generating a detection signal upon detecting a predetermined level of the input signal; buffer means connected between the first power terminal and the Schmitt trigger means for receiving said detection signal; a first transistor having drain, source and gate terminals, said drain terminal thereof connected to the input terminal; a second transistor having drain, source and gate terminals, said drain terminal thereof connected to said gate terminal of said first transistor, said gate terminal thereof connected to the first power terminal and said source terminal thereof connected to said buffer means; third and fourth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming a first node therebetween, said gate terminal of said third transistor being connected to said source terminal of said first transistor and said gate terminal of said fourth transistor being connected to said source terminal of said second transistor; capacitor means connected between said source terminal of said first transistor and said first node; and fifth and sixth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming the output terminal therebetween, said gate terminal of said fifth transistor connected to said gate terminal of said third transistor and said gate terminal of said sixth transistor connected to said gate terminal of said fourth transistor.

Claim 18

A clock generator circuit for producing clocking signals wherein the clock generator circuit receives an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals, comprising: Schmitt trigger means connected between the first and second power terminals and to the input terminal for receiving the input signal and for generating a detection signal upon detecting a predetermined level of the input signal; buffer means connected between the first power terminal and the Schmitt trigger means for receiving said detection signal; a first transistor having drain, source and gate terminals, said drain terminal thereof connected to the input terminal; a second transistor having drain, source and gate terminals, said drain terminal thereof connected to said gate terminal of said first transistor, said gate terminal thereof connected to the first power terminal and said source terminal thereof connected to said buffer means; third and fourth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming a first node therebetween, said gate terminal of said third transistor being connected to said source terminal of said first transistor and said gate terminal of said fourth transistor being connected to said source terminal of said second transistor; capacitor means connected between said source terminal of said first transistor and said first node; and fifth and sixth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming the output terminal therebetween, said gate terminal of said fifth transistor connected to said gate terminal of said third transistor and said gate terminal of said sixth transistor connected to said gate terminal of said fourth transistor.

Claim 19

The clock generator circuit of claim 14 wherein said buffer means comprises push-pull inverter means.

Claim 20

The clock generator circuit of claim 14 wherein said Schmitt trigger means comprises: seventh, eighth and ninth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming a second node between said seventh and eighth transistors and a third node between said eighth and ninth transistors; and a tenth transistor having drain, source and gate terminals connected between the first power terminal and said third node and said gate terminal thereof connected to said second node.

Claim 21

The clock generator circuit of claim 16 wherein said buffer means comprises: eleventh and twelfth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and said third node and forming a fourth node therebetween, said gate terminal of said eleventh transistor connected to said second node, said gate terminal of said twelfth transistor being connected to the input terminal; and said fourth node being connected to said source terminal of said second transistor and to said gate terminals of said fourth and sixth transistors.

Claim 22

A clock generator circuit for producing clocking signals which receives an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals, comprising: first, second and third transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming a first node between said first and second transistors and a second node between said second and third transistors; a fourth transistor having drain, source and gate terminals connected between the first power terminal and said second node, said gate terminal thereof connected to said first node; fifth and sixth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and said second node, and forming a third node therebetween, said gate terminal of said fifth transistor connected to said first node; said gate terminal of said second transistor, said gate terminal of said third transistor and said gate terminal of said sixth transistor being connected to the input terminal; a seventh transistor having drain, source and gate terminals, said drain terminal thereof connected to the input terminal; an eighth transistor having drain, source and gate terminals, said drain terminal thereof connected to said gate terminal of said seventh transistor, said gate terminal thereof connected to the first power terminal and said source terminal thereof connected to said third node; ninth and tenth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming a fourth node therebetween, said gate terminal of said ninth transistor being connected to said source terminal of said seventh transistor and said gate terminal of said tenth transistor being connected to said source terminal of said eighth transistor; capacitor means connected between said source terminal of said seventh transistor and said fourth node; and eleventh and twelfth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming the output terminal therebetween, said gate terminal of said eleventh transistor connected to said gate terminal of said ninth transistor and said gate terminal of said twelfth transistor connected to said gate terminal of said tenth transistor.

Claim 23

A clock generator circuit for producing clocking signals which receives an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals, comprising: first, second and third transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming a first node between said first and second transistors and a second node between said second and third transistors; a fourth transistor having drain, source and gate terminals connected between the first power terminal and said second node, said gate terminal thereof connected to said first node; fifth and sixth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and said second node, and forming a third node therebetween, said gate terminal of said fifth transistor connected to said first node; said gate terminal of said second transistor, said gate terminal of said third transistor and said gate terminal of said sixth transistor being connected to the input terminal; a seventh transistor having drain, source and gate terminals, said drain terminal thereof connected to the input terminal; an eighth transistor having drain, source and gate terminals, said drain terminal thereof connected to said gate terminal of said seventh transistor, said gate terminal thereof connected to the first power terminal and said source terminal thereof connected to said third node; ninth and tenth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming a fourth node therebetween, said gate terminal of said ninth transistor being connected to said source terminal of said seventh transistor and said gate terminal of said tenth transistor being connected to said source terminal of said eighth transistor; capacitor means connected between said source terminal of said seventh transistor and said fourth node; and eleventh and twelfth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming the output terminal therebetween, said gate terminal of said eleventh transistor connected to said gate terminal of said ninth transistor and said gate terminal of said twelfth transistor connected to said gate terminal of said tenth transistor.

Claim 24

The clock generator circuit of claim 18 wherein said first transistor comprises a depletion type MOSFET.

Claim 25

The clock generator circuit of claim 18 wherein said first transistor comprises a saturated enhancement type MOSFET, said gate terminal thereof being connected to the first power terminal.

Claim 26

The clock generator circuit of claim 18 wherein said second, third, fourth and sixth transistors comprise enhancement type MOSFETs.

Claim 27

The clock generator circuit of claim 18 wherein said fifth transistor comprises a MOSFET having a threshold voltage of approximately zero volts.

Claim 28

The clock generator circuit of claim 18 wherein said first, second, third and fourth transistors comprise a Schmitt trigger stage and said fifth and sixth transistors comprise a push-pull inverter stage to prevent capacitive loading of said Schmitt trigger stage.

Claim 29

The clock generator of claim 18 and further including reset means.

Claim 30

The clock generator of claim 24 wherein said reset means includes: thirteenth and fourteenth transistors each having drain, source and gate terminals, said gate terminal of said thirteenth transistor connected to the first power terminal, said drain terminal of said thirteenth transistor connected to said gate terminal of said ninth transistor, said source terminal of said thirteenth transistor connected to said drain terminal of said fourteenth transistor, said source terminal of said fourteenth transistor connected to the second power terminal, and said gate terminal of said fourteenth transistor forming a reset terminal; and a fifteenth transistor having drain, source and gate terminals, said drain terminal connected to the output terminal, said source terminal thereof connected to the second power terminal and said gate terminal thereof connected to said reset terminal.