Clock pulse amplifier and clipper

Claim 2

A voltage regulator circuit comprising: clock input means for supplying a clock input signal having a predetermined first voltage range; sensing means connected to said clock input means for detecting the voltage level of said clock input signal; regulating means having an input connected to said sensing means and an output, said regulating means functioning to reduce said predetermined first voltage range of said clock signal to a smaller second voltage range; and clock output means connected to said output of said regulating means for producing a clock output signal having said second voltage range, said regulating means functions to substantially linearly proportionally reduce the amplitude V of said input signal in the range V o <V<V 1 , and to clip the amplitude of said input signal in the range V>V 1 to substantially constant values αV 1 , where V o and V 1 are predetermined constants within said first voltage range, and 0<α<1.

Claim 3

A circuit as defined in claim 1, further comprising: means for applying a first relatively positive and second relatively negative potential to said circuit, wherein said sensing means comprises first and second multiterminal semiconductor devices connected in electrical series between said first and said second potentials.

Claim 4

A circuit as defined in claim 2, wherein each of said multiterminal semiconductor devices is a field effect transistor.

Claim 5

A circuit as defined in claim 2, wherein said regulating means comprises third and fourth multiterminal semiconductor devices each having their control electrode connected to the node between said first and second semiconductor devices.

Claim 6

A circuit as defined in claim 4, wherein said third and fourth multiterminal semiconductor devices are field effect transistors.

Claim 7

A circuit as defined in claim 2 further comprising voltage reference means having an output connected to the control electrode of one of said semiconductor devices for providing a predetermined voltage reference for said sensing means.

Claim 8

A circuit as defined in claim 6, wherein said voltage reference means comprises a plurality of multiterminal semiconductor devices connected in electrical series between said first and said second potentials.

Claim 9

A circuit as defined in claim 7, wherein said voltage reference means comprises a plurality of field effect transistors having respective conduction path terminals and a control terminal, including a first depletion mode field effect transistor having a first conduction path terminal connected to said first potential, and a second conduction path terminal connected to its control terminal; a second depletion mode field effect transistor having a first conduction path terminal connected to said second conduction path terminal of said first depletion mode field effect transistor, and a second conduction path terminal connected to its control terminal and to said output.

Claim 10

A circuit as defined in claim 8, further comprising a first enhancement mode field effect transistor having a first conduction path terminal connected to said output, and a control terminal connected to said control terminal of said first depletion mode field effect transistor, and a second enhancement mode field effect transistor having a first conduction path terminal connected to said second conduction path terminal, second conduction path terminal connected to said second source of potential, and a control terminal connected to said output.

Claim 11

A regulator circuit having an input terminal for supplying an input clock signal having a predetermined first voltage range, an output terminal, a first source of relatively positive and a second source of relatively negative electrical potential, and a voltage reference input, said circuit comprising: a plurality of multi-terminal semiconductor means having respective conduction path terminals and a control terminal and interconnected between said input and output terminals, including a first depletion mode FET having one conduction path terminal connected to said first source of electrical potential, the other conduction path terminal connected to a first intermediate node, and its control terminal connected to a second intermediate node; a first enhancement mode FET having one conduction path terminal connected to said first intermediate node, the other conduction path terminal connected to said second source of electrical potential, and its control terminal connected to said voltage reference input; a second enhancement mode FET having one conduction path terminal connected to said second intermediate node, the other conduction path terminal connected to said second source of potential, and its control electrode connected to said first intermediate node; and a third enhancement mode FET having one conduction path terminal connected to said input terminal, the other conduction path terminal connected to said second source of potential, and its control electrode connected to said first intermediate node; said second intermediate node functioning to control said output terminal for producing an output clock signal thereon corresponding in phase and duration to said input clock signal; said second and third FETs functioning to regulate the amplitude of the signal at said second intermediate node so that the clock signal produced on said output terminal has a voltage range limited to a predetermined second range smaller than said first range.

Claim 12

A regulator circuit having an input terminal for supplying an input clock signal having a predetermined first voltage range, an output terminal, a first source of relatively positive and a second source of relatively negative electrical potential, and a voltage reference input, said circuit comprising: a plurality of multi-terminal semiconductor means having respective conduction path terminals and a control terminal and interconnected between said input and output terminals, including a first depletion mode FET having one conduction path terminal connected to said first source of electrical potential, the other conduction path terminal connected to a first intermediate node, and its control terminal connected to a second intermediate node; a first enhancement mode FET having one conduction path terminal connected to said first intermediate node, the other conduction path terminal connected to said second source of electrical potential, and its control terminal connected to said voltage reference input; a second enhancement mode FET having one conduction path terminal connected to said second intermediate node, the other conduction path terminal connected to said second source of potential, and its control electrode connected to said first intermediate node; and a third enhancement mode FET having one conduction path terminal connected to said input terminal, the other conduction path terminal connected to said second source of potential, and its control electrode connected to said first intermediate node; said second intermediate node functioning to control said output terminal for producing an output clock signal thereon corresponding in phase and duration to said input clock signal; said second and third FETs functioning to regulate the amplitude of the signal at said second intermediate node so that the clock signal produced on said output terminal has a voltage range limited to a predetermined second range smaller than said first range.

Claim 13

A circuit as defined in claim 10, wherein said second and third FETs function to substantially lineary proportionally reduce the amplitude V of said input signal in the range V o <V<V 1 , and to clip the amplitude of said input signal in the range V>V 1 to a substantially constant value αV 1 , where V o and V 1 are predetermined constants within said first voltage range, and o<α<1.