Double bootstrapped clock buffer circuit

Claim 1

A buffer circuit, operatively connected to a supply voltage and to receive an input signal, producing an output signal in response to the input signal, comprising: first and second output transistors having their drain-source current paths operatively connected in series between the supply voltage and ground, thereby forming a junction between said first and second output transistors, each of said first and second output transistors having a gate; an output terminal operatively connected to the junction between said first and second output transistors; a first boot-strap circuit operatively connected to the gate of said first output transistor for charging the gate of said first output transistor to a charged voltage above the supply voltage when the input signal has a first logic level, turning on said first output transistor and charging said output terminal to the supply voltage, said first boot-strap circuit comprising: a capacitor operatively connected to the gate of said first output transistor; and a precharging transistor, having its drain-source current path coupled between the supply voltage and saidcapacitor, for precharging said capacitor and having a gate; and a second boot-strap circuit having an output node operatively connected to the gate of said precharging transistor in said first boot-strap circuit, for driving the gate of said precharging transistor to a precharged voltage above the supply voltage when the input signal has a second logic level.