Rhodium capped gold IC metallization

Claim 2

A metallization process for interconnecting elements on a integrated circuit chip, comprising: forming electrical contact openings in a first, surface dielectric layer on the chip; depositing a first metallization on the first dielectric layer in accordance with a first predetermined pattern, including into said contact openings, the first metallization having sidewalls generally normal to the first dielectric layer; annealing the chip at a temperature T sufficient to relieve mechanical stresses in the metallization; depositing a second dielectric layer on the chip to cover the first dielectric and the first metallization including the sidewalls thereof; and depositing a second metallization on the second dielectric in accordance with a second predetermined pattern, including a contact electrically interconnecting the second metallization and a portion of the first metallization and a conduction line at a predetermined spacing from one of the sidewalls of the first metallization; the step of depositing the first metallization including sequentially depositing a layer of a first metal onto the first dielectric and into the contact openings and a layer of a second metal atop the first metal and extending to edges coextensive with said sidewalls; the first metal being a highly conductive metal having a first rigidity characteristic and the second metal having a second rigidity characteristic, such that the second metal is more rigid than the first metal at annealing temperature T and thereby maintains the first metallization through annealing in a shape substantially as deposited.

Claim 3

A process according to claim 1 in which the rigidity characteristics of the first and second metals vary with temperature and at annealing temperature T the second metal has a T/T M2 ratio less than the ratio T/T M1 , where T M1 and T M2 are the melting temperatures of the first and second metals, respectively.

Claim 4

A process according to claim 1 in which the first and second metals each have a characteristic resistivity, the resistivity of the first metal being less than that of the second metal, the depositing step including depositing each of the first and second metals to a predetermined thickness, the thickness of the layer of second metal being substantially less than the thickness of the layer of the first metal.

Claim 5

A process according to claim 3 in which the first and second metals have an interdiffusivity at annealing temperature such that they are mutually adherent but low enough at annealing temperature T that diffusion of the second metal into the first metal is limited to a small fraction of the thickness of the layer of first metal.

Claim 6

A process according to claim 1 in which the first and second metals are corrosion-resistant metals and are addivitively deposited.

Claim 7

A process according to claim 1 in which the first and second metals are electrodeposited.

Claim 8

A process according to claim 1 in which at least the second metal is corrosion- and oxidation-resistant, the second metal being deposited on the first metal before oxidation or corrosion of the first metal can occur.

Claim 9

A process according to claim 1 in which the sequential deposition step includes electrodepositing one of gold, silver and copper as said first metal and electrodepositing one of rhodium and platinum as the second metal.

Claim 10

A process according to claim 8, in which the first metal is silver or copper, including electrodepositing the second metal before the first metal can corrode or oxidize.

Claim 11

A process according to claim 8 in which the first metal is gold and the secod metal is rhodium.

Claim 12

A process according to claim 8 in which the first metal is electrodeposited to a first thickness; the second metal is electrodeposited to a second thickness less by an order of magnitude than the first thickness; and annealing temperature T is limited to a temperature at which diffusion of the first metal into the second metal is less by an order of magnitude than the second thickness.

Claim 13

A metallization process for interconnecting elements on a integrated circuit chip, comprising: forming electrical contact openings in a first, surface dielectric layer on the chip; depositing a first metallization on the first dielectric layer in accordance with a first predetermined pattern, including into said contact openings, the first metallization having sidewalls generally normal to the first dielectric layer; annealing the chip at a temperature T sufficient to relieve mechanical stresses in the metallization; depositing a second dielectric layer on the chip to cover the first dielectric and the first metallization including the sidewalls thereof; and depositing a second metallization on the second dielectric in accordance with a second predetermined pattern, including a contact electrically interconnecting the second metallization and a portion of the first metallization and a conduction line at a predetermined spacing from one of the sidewalls of the first metallization; the step of depositing the first metallization including sequentially depositing a layer of a first metal onto the first dielectric and into the contact openings and a layer of a second metal atop the first metal and extending to edges coextensive with said sidewalls; the first metal being a Group IB metal and the second metal being a corrosion- and oxidation-resistant platinum group metal; the sequential deposition of the first and second metals being arranged so that the second metal is deposited on the first metal in the substantial absence of oxidation and corrosion thereon, thereby providing a corrosion and oxidation free contact for the second metallization.

Claim 14

A metallization process for interconnecting elements on a integrated circuit chip, comprising: forming electrical contact openings in a first, surface dielectric layer on the chip; depositing a first metallization on the first dielectric layer in accordance with a first predetermined pattern, including into said contact openings, the first metallization having sidewalls generally normal to the first dielectric layer; annealing the chip at a temperature T sufficient to relieve mechanical stresses in the metallization; depositing a second dielectric layer on the chip to cover the first dielectric and the first metallization including the sidewalls thereof; and depositing a second metallization on the second dielectric in accordance with a second predetermined pattern, including a contact electrically interconnecting the second metallization and a portion of the first metallization and a conduction line at a predetermined spacing from one of the sidewalls of the first metallization; the step of depositing the first metallization including sequentially depositing a layer of a first metal onto the first dielectric and into the contact openings and a layer of a second metal atop the first metal and extending to edges coextensive with said sidewalls; the first metal being a Group IB metal and the second metal being a corrosion- and oxidation-resistant platinum group metal; the sequential deposition of the first and second metals being arranged so that the second metal is deposited on the first metal in the substantial absence of oxidation and corrosion thereon, thereby providing a corrosion and oxidation free contact for the second metallization.

Claim 15

A process according to claim 12 in which the sequential deposition step includes electrodepositing one of gold, silver and copper as said first metal and electrodepositing one of rhodium and platinum as the second metal.

Claim 16

A two-layer integrated circuit metallization process comprising: providing a substrate having reference surface; forming a first dielectric layer on the reference surface; forming contact openings in the dielectric to expose portions of the chip surface in predetermined circuit locations; depositing a conductive barrier layer over the dielectric layer and the exposed portions of the chip surface; applying a mask over the barrier layer and patterning the mask to expose selected portions of the barrier layer including within said contact openings and adjacent thereto; electrodepositing a first metal layer onto the exposed portions of the conductive barrier layer, the first metal consisting essentially of a Group IB metal; electrodepositing a second metal layer atop the first metal layer, the second metal consisting essentially of a platinum group metal; removing the mask so as to expose a sidewall of the electrodeposited first and second metal layers and to expose an adjoining region of the barrier layer; annealing the substrate including said first and second metals, the first and second metal layers together defining a first metallization of the integrated circuit; selectively etching away the barrier layer in said adjoining region to expose the underlying first dielectric layer; depositing a second dielectric layer so as to cover the second metal, the sidewall of first metallization, and the adjoining regions of the first dielectric layer; and forming a second metallization on the second dielectric layer, including a via on a portion of the first metallization and a conductive line extending alongside said portion at a predetermined spacing from said sidewall.

Claim 17

A two-layer integrated circuit metallization process comprising: providing a substrate having reference surface; forming a first dielectric layer on the reference surface; forming contact openings in the dielectric to expose portions of the chip surface in predetermined circuit locations; depositing a conductive barrier layer over the dielectric layer and the exposed portions of the chip surface; applying a mask over the barrier layer and patterning the mask to expose selected portions of the barrier layer including within said contact openings and adjacent thereto; electrodepositing a first metal layer onto the exposed portions of the conductive barrier layer, the first metal consisting essentially of a Group IB metal; electrodepositing a second metal layer atop the first metal layer, the second metal consisting essentially of a platinum group metal; removing the mask so as to expose a sidewall of the electrodeposited first and second metal layers and to expose an adjoining region of the barrier layer; annealing the substrate including said first and second metals, the first and second metal layers together defining a first metallization of the integrated circuit; selectively etching away the barrier layer in said adjoining region to expose the underlying first dielectric layer; depositing a second dielectric layer so as to cover the second metal, the sidewall of first metallization, and the adjoining regions of the first dielectric layer; and forming a second metallization on the second dielectric layer, including a via on a portion of the first metallization and a conductive line extending alongside said portion at a predetermined spacing from said sidewall.

Claim 18

A process according to claim 14, in which the first metal is silver or copper, including electrodepositing the second metal before the first metal can corrode or oxidize.

Claim 19

A process according to claim 14 in which the first metal is gold and the second metal is rhodium.

Claim 20

A process according to claim 14 in which the first metal is electrodeposited to a first thickness; the second metal is electrodeposited to a second thickness less by an order of magnitude than the first thickness; and annealing temperature is limited to a temperature at which diffusion of the second metal into the first metal is less by an order of magnitude than the second thickness.