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US4182781A Expired / Lapsed US ⏱️ 0.0 years remaining

Low cost method for forming elevated metal bumps on integrated circuit bodies employing an aluminum/palladium metallization base for electroless plating

Assignee: Texas Instruments Inc
•
Filing: 1977-09-21
•
Granted: 1980-01-08
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Expires: 1997-09-21
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Abstract

Abstract Elevated metal contact bumps are provided on a microelectronic semiconductor circuit, with the use of aluminum-palladium metallization as a base for selective electroless plating. The aluminum and palladium are preferably deposited sequentially in a single operation, i.e., without exposing the aluminum surface to the atmosphere. The aluminum-palladium film is then patterned in a single step, using an etchant which attacks both metals at substantially the same rate. The metal pattern is then covered with an insulation layer wherein apertures are opened to expose palladium at selected sites for immersion in an electroless plating bath of ionic Cu or Ni for bump formation.

Inventors

  • 👤 Robert C. Hooper
  • 👤 Alexander J. Harrover
  • 👤 Michael J. VanHoy
  • 👤 Charles E. Terry

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 04:56
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/01; H10W72/012; H10W72/019; H10W72/20; H10W72/251; H10W72/252; H10W72/255; H10W72/90; H10W72/921; H10W72/923; H10W72/951; H10W72/952

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 125 words
A method for the metallization of a semiconductor integrated circuit, comprising the steps of: (a) forming an insulation layer on the semiconductor, said layer having apertures at locations for ohmic contact to said semiconductor; (b) sequentially depositing a thin film of aluminum and a thin film of palladium on said layer and in said apertures; (c) patterning both said films; in a single step (d) covering the resulting pattern with a second layer of insulation, and patterning to provide said second layer apertures which selectively expose palladium at locations on said pattern where metal bumps are desired; then (e) plating the exposed palladium with a suitable metal for bump formation, by electroless plating and continuing the plating until a bump of sufficient height is formed.
Claim 2
Independent Claim 125 words
A method for the metallization of a semiconductor integrated circuit, comprising the steps of: (a) forming an insulation layer on the semiconductor, said layer having apertures at locations for ohmic contact to said semiconductor; (b) sequentially depositing a thin film of aluminum and a thin film of palladium on said layer and in said apertures; (c) patterning both said films; in a single step (d) covering the resulting pattern with a second layer of insulation, and patterning to provide said second layer apertures which selectively expose palladium at locations on said pattern where metal bumps are desired; then (e) plating the exposed palladium with a suitable metal for bump formation, by electroless plating and continuing the plating until a bump of sufficient height is formed.
Claim 3
Dependent Claim 19 words
A method is in claim 1 wherein said semiconductor is silicon, and said first insulation layer is silicon oxide.
Claim 4
Dependent Claim 23 words
A method is in claim 1 wherein said step of patterning the aluminum-palladium film includes selectively etching with acetic, phosphoric and nitric acids.
Claim 5
Dependent Claim 28 words
A method as in claim 1 wherein said second layer of insulation is formed by plasma-assisted chemical vapor deposition of SiO 2 and SI 3 N 4 .
Claim 6
Dependent Claim 28 words
A method as in claim 1 wherein said plating step includes immersion of the exposed palladium in an electroless plating bath of an ionic Ni or Cu compound.
Claim 7
Dependent Claim 20 words
A method as in claim 1 further including the step of coating the resulting bump with a layer of gold.
Claim 8
Dependent Claim 33 words
A method as in claim 1 wherein the resist pattern used for forming apertures in the second layer of insulation is left in place during the subsequent plating step to form metal bumps.

References Cited (Backward Citations)

US3239376A Cited
US3453501A Cited
US3623961A Cited
US3597834A Cited
US3579375A Cited
US3663184A Cited
US3669734A Cited
US4005472A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1983-01-07 1983-07-09 1984-01-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1987-01-07 1987-07-09 1988-01-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1991-01-07 1991-07-09 1992-01-08 $7700.00 Window Closed / Lapsed

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