Patent US3754947A successfully refreshed from Google Patents.
Patent US4680733A successfully refreshed from Google Patents.
US4680733A
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Device for serializing/deserializing bit configurations of variable length
Assignee: International Business Machines Corp
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Filing: 1984-10-29
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Granted: 1987-07-14
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Expires: 2004-10-29
Abstract
Abstract A serdes device includes circuitry for loading or reading bit configurations into or out of strings of latches of variable length nk+r, where n is the number of bits in a byte, k is the number of whole bytes and r is the number of residual bits, with r being smaller than n. Under the control of a service processor (8), there is formed a ring comprised of the latches of the serializer/deserializer register (14), the latches of the string considered (3 or 4) and a selected number (n-r) of latches of an extension register (16). The bytes to be loaded are sequentially sent to register (14), starting with the byte that contains the residual bits, and n bits are shifted out after loading each successive byte, so that after k+1 shifts the desired configuration will be contained in the string. For reading the contents of a string (for example, string 3), n bits are shifted, register (14) is read out, then k shifts of n bits each are performed, with register (14) being read out after each shift.
Inventors
- 👤 Guy G. Duforestel
- 👤 Michel A. Lechaczynski
- 👤 Clement Y. Poiraud
- 👤 Paul P. Viallon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:50
CPC Classifications
G; G11; G11C; G11C19/00; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31712; G01R31/31715; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541; G01R31/319; G01R31/31903; G01R31/31908; G01R31/31917; G01R31/31919; H; H03; H03M; H03M9/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
64 words
A serializer/deserializer device for loading bit configurations comprising strings of latches of variable length nk+r, where n is the number of bits in a byte, k is the number of whole bytes in the string, and r is the number of residual bits, with r being smaller than n, and n being greater than 1, characterized said serializer/deserializer device in that it further comprises:
Claim 2
Dependent Claim
64 words
A serializer/deserializer device for loading bit configurations comprising strings of latches of variable length nk+r, where n is the number of bits in a byte, k is the number of whole bytes in the string, and r is the number of residual bits, with r being smaller than n, and n being greater than 1, characterized said serializer/deserializer device in that it further comprises:
Claim 3
Dependent Claim
242 words
a serializer/deserializer (SERDES) shift register (14) having n latches that can be loaded in parallel, an extension register (16) having (n-1) latches, said extension register and said SERDES shift register being connected in series; selection means (18, 22, 24) for forming in said extension register a shift register the number of selected latches of which will vary dependent upon the length of the string of such that the number of selected latches is equal to (n-r), means (36, 38, 46, 48, 44, 32) for interconnecting the latches of the SERDES register, those of the string of latches, and ones of the extension register latches selected by said selection means to form a register, such that bits can be circulatorily shifted serially from said SERDES shift register and said extension register to said string of latches; means (6, 8, 20-W) for sequentially writing into the SERDES register the bytes to be loaded in the string of latches, and clock and writing means (26, 40, 20-W) for selectively applying to the latches in said ring network clock pulses causing the bits in the ring network to be shifted, to load in parallel in the SERDES register the byte that includes the residual bits, in the low order bit positions of the byte cause n bits to be shifted in the ring network, load the k bytes in succession in the SERDES shift register, and cause n bits to be shifted after loading each byte.
Claim 4
Dependent Claim
242 words
a serializer/deserializer (SERDES) shift register (14) having n latches that can be loaded in parallel, an extension register (16) having (n-1) latches, said extension register and said SERDES shift register being connected in series; selection means (18, 22, 24) for forming in said extension register a shift register the number of selected latches of which will vary dependent upon the length of the string of such that the number of selected latches is equal to (n-r), means (36, 38, 46, 48, 44, 32) for interconnecting the latches of the SERDES register, those of the string of latches, and ones of the extension register latches selected by said selection means to form a register, such that bits can be circulatorily shifted serially from said SERDES shift register and said extension register to said string of latches; means (6, 8, 20-W) for sequentially writing into the SERDES register the bytes to be loaded in the string of latches, and clock and writing means (26, 40, 20-W) for selectively applying to the latches in said ring network clock pulses causing the bits in the ring network to be shifted, to load in parallel in the SERDES register the byte that includes the residual bits, in the low order bit positions of the byte cause n bits to be shifted in the ring network, load the k bytes in succession in the SERDES shift register, and cause n bits to be shifted after loading each byte.
Claim 5
Dependent Claim
119 words
A device according to claim 1, used to read bits contained in a string of latches of length nk+r, characterized in that it comprises means (8, 20-R) for reading out the contents of the SERDES register, the bits contained in the string of latches being read out by performing a first shift of n bits in the ring register comprising the latches of the SERDES register, the string of latches to read out and (n-r) latches of the extension register, by reading out the contents of the latches in the SERDES register, by causing k successive shifts of n bits to be performed, and by reading out the contents of the SERDES register after each shift of n bits.
Claim 6
Dependent Claim
38 words
A device according to claim 2, characterized in that it is used for writing and reading data into and out of strings of latches formed in a data processing unit in order to test and initialize said unit.
Claim 7
Dependent Claim
199 words
A device according to claim 3, characterized in that said means for writing and reading bytes into and out of the SERDES register include a microprocessor (8) associated with a memory (6) an area of which is allocated to each string of the unit for storing the outgoing bit configurations arranged into bytes as well as the number of residual bits relating to the string, said microprocessor comprising: an input/output bus (20) through which the bits stored in the memory are transferred to the SERDES register by means of a write operation, the bits stored in the SERDES register are transferred to the microprocessor by means of a read operation, and the number of residual bits is sent to the selection means to select the (n-r) latches of the extension register, a string address line (30) for interconnecting the selected string of latches, the SERDES register and the selected latches of the extension register to form a ring register, and a shift control line (28) for causing the number of clock pulses required to effect n-bit shifts to be applied at appropriate times to the latches in the ring register formed after a string of latches has been addressed.
Claim 8
Independent Claim
102 words
A device according to any one of claims 2 to 4, characterized in that the selection means includes: a register (18) into which the number of residual bits for the string to be loaded or read out is written, a decoding circuit (22) for decoding the contents of said register, said circuit having n outputs (R0 to R7) and generating an active signal on one of the outputs depending on the contents of the register, and selection logic (FIG. 5A) that receives the outputs from the decoding circuit (22) to cause (n-r) latches of the extension register to be connected in series.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-13 | 1991-01-12 | 1991-07-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-13 | 1995-01-12 | 1995-07-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-13 | 1999-01-12 | 1999-07-14 | $7700.00 | Window Closed / Lapsed |