Circuit and method for producing accurate dc restored video waveform, horizontal sync pulses, and vertical sync pulses

Claim 3

The method of claim 1 including applying the output of the first monostable multivibrator to the input of a second monostable multivibrator that produces output pulses wider than the output pulses produced by the first monostable multivibrator, and performing a logical ANDing function on the output of the second monostable multivibrator and the output of the first monostable vibrator to produce a jitter-free horizontal sync signal.

Claim 4

The method of claim 2 including applying the vertical sync signal to the clock input of a second latch and applying the output of the second monostable multivibrator to the input of the second latch to produce a jitter-free frame sync signal.

Claim 5

The method of claim 3 wherein the first and second latches are D-type latches.

Claim 6

The method of claim 3 wherein the logical ANDing step includes applying the output of the first monostable multivibrator and the logical complement of the output of the second monostable multivibrator to the input of a circuit that performs a logical NANDing function to inhibit half line pulses of the composite sync signal and to thereby produce the horizontal sync signal.

Claim 7

The method of claim 3 wherein the width of the pulses produced by the first monostable multivibrator is greater than incoming horizontal pulse widths is less than about three-fourths of a the duration of a horizontal line.

Claim 8

The method of claim 3 wherein step (d) includes applying the second signal to an input of a sample and hold circuit and strobing the sample and hold circuit by performing a logical AND operation on the composite sync signal and the output of the first monostable multivibrator.

Claim 9

The method of claim 1 including applying the second DC reference voltage to the positive input of a third differential amplifier and coupling the second signal to a negative input of the third differential amplifier to produce a DC restored video signal wherein the voltages of its back porch portions have a fixed relationship to the ground reference voltage.

Claim 12

A video circuit comprising: (a) a first differential amplifier; (b) a negative-sensing peak sense and hold circuit; (c) means for applying a first signal, which is a composite video signal, to a negative input of the first differential amplifier and an input of the negative-sensing peak sense and hold circuit to cause the negative-sensing peak sense and hold circuit to produce a first DC reference voltage that is equal to the negative sync tip voltage of the first signal; (d) means for applying the first DC reference voltage to the positive input of the first differential amplifier to cause the first differential amplifier to produce a second signal that is an inverted replica of the first signal and has its level shifted so that the voltage of a sync tip portion of the second signal is equal to a ground reference voltage; (e) a second differential amplifier; (f) means for applying the second signal to a negative input of a second differential amplifier; (g) means for sensing the voltage of the second signal during a back porch portion thereof and producing a second DC reference voltage representative of the voltage of the back porch portion of the second signal; (h) a comparator; (i) means for applying the second DC reference voltage to the positive input of the second differential amplifier and a fraction of the second DC voltage to the positive input of a comparator; (j) means for coupling the output of the second differential amplifier through a diode to the negative input of the comparator to cause the comparator to produce a composite sync signal containing a series of narrow negative going pulses during a pre-equalization portion thereof followed by a plurality of narrow serration pulses during a vertical sync pulse interval portion thereof; (k) a first monostable multivibrator and a first latch; (l) means for applying the composite sync signal to a first monostable multivibrator and causing an output of the first monostable multivibrator to produce pulses which are wider than the narrow negative-going pulses during the pre-equalization period of the composite sync signal but narrower than the interval between the serration pulses; and (m) means for clocking the first latch with a trailing edge of the output pulses produced by the first monostable multivibrator in order to produce a jitter-free vertical sync signal that undergoes a jitter-free transition in response to a transition between the pre-equalization portion and the vertical sync pulse interval portion of the composite sync signal.

Claim 13

A video circuit comprising: (a) a first differential amplifier; (b) a negative-sensing peak sense and hold circuit; (c) means for applying a first signal, which is a composite video signal, to a negative input of the first differential amplifier and an input of the negative-sensing peak sense and hold circuit to cause the negative-sensing peak sense and hold circuit to produce a first DC reference voltage that is equal to the negative sync tip voltage of the first signal; (d) means for applying the first DC reference voltage to the positive input of the first differential amplifier to cause the first differential amplifier to produce a second signal that is an inverted replica of the first signal and has its level shifted so that the voltage of a sync tip portion of the second signal is equal to a ground reference voltage; (e) a second differential amplifier; (f) means for applying the second signal to a negative input of a second differential amplifier; (g) means for sensing the voltage of the second signal during a back porch portion thereof and producing a second DC reference voltage representative of the voltage of the back porch portion of the second signal; (h) a comparator; (i) means for applying the second DC reference voltage to the positive input of the second differential amplifier and a fraction of the second DC voltage to the positive input of a comparator; (j) means for coupling the output of the second differential amplifier through a diode to the negative input of the comparator to cause the comparator to produce a composite sync signal containing a series of narrow negative going pulses during a pre-equalization portion thereof followed by a plurality of narrow serration pulses during a vertical sync pulse interval portion thereof; (k) a first monostable multivibrator and a first latch; (l) means for applying the composite sync signal to a first monostable multivibrator and causing an output of the first monostable multivibrator to produce pulses which are wider than the narrow negative-going pulses during the pre-equalization period of the composite sync signal but narrower than the interval between the serration pulses; and (m) means for clocking the first latch with a trailing edge of the output pulses produced by the first monostable multivibrator in order to produce a jitter-free vertical sync signal that undergoes a jitter-free transition in response to a transition between the pre-equalization portion and the vertical sync pulse interval portion of the composite sync signal.

Claim 14

The video circuit of claim 10 including a second monostable multivibrator and means for applying the output of the first monostable multivibrator to the input of a second monostable multivibrator and causing it to produce output pulses wider than the output pulses produced by the first monostable multivibrator, and means for performing a logical ANDing function on the output of the second monostable multivibrator and the output of the first monostable vibrator to produce a jitter-free horizontal sync signal.

Claim 15

The video circuit of claim 11 including a second latch and means for applying the vertical sync signal to the clock input of the second latch and applying the output of the second monostable multivibrator to the input of the second latch to produce a jitter-free frame sync signal.

Claim 16

The video circuit of claim 12 wherein the first and second latches are D-type latches.

Claim 17

The video circuit of claim 12 wherein the logical ANDing means includes means for applying the output of the first monostable multivibrator and the logical complement of the output of the second monostable multivibrator to the input of a circuit that performs a logical NANDing function to inhibit half line pulses of the composite sync signal and to thereby produce the horizontal sync signal.

Claim 18

The video circuit of claim 12 wherein the width of the pulses produced by the first monostable multivibrator is greater than incoming horizontal pulse widths is less than about three-fourths of a the duration of a horizontal line.

Claim 19

The video circuit of claim 12 wherein the sensing means includes a sample and hold circuit and means for applying the second signal to an input of a sample and hold circuit and strobing the sample and hold circuit by performing a logical AND operation on the composite sync signal and the output of the first monostable multivibrator.

Claim 20

The video circuit of claim 10 including a third differential amplifier and means for applying the second DC reference voltage to the positive input of the third differential amplifier and means for coupling the second signal to a negative input of the third differential amplifier to produce a DC restored video signal wherein the voltages of its back porch portions have a fixed relationship to the ground reference voltage.