Sync separator circuit

Claim 2

A sync separator circuit, comprising: a source of video signals, said video signals including synchronizing signals; a first plurality of series coupled diodes; controllable switching means coupled to said first plurality; a source of first bias current coupled to a control terminal of said controllable switching means; first means coupled to one of said first plurality and said controllable switching means for providing a first current through said first plurality of series coupled diodes, said first current establishing a first voltage at a first terminal coupled to said first plurality of series coupled diodes during the occurrence of said synchronizing signals; second means coupled to said control terminal and responsive to said source of video signals for providing during the occurrence of said synchronizing signals an additional bias current to said controllable switching means for introducing to said first plurality of series coupled diodes during said occurrence a second current in addition to said first current for establishing a second voltage at said first terminal; a source of first reference voltage; and comparator means responsive to said first reference voltage and said second voltage for developing an output signal when said second voltage and said first reference voltage differ by a predetermined value.

Claim 3

A circuit according to claim 1, wherein said source of first reference voltage comprises a second plurality of series coupled diodes through which a third current flows.

Claim 4

A circuit according to claim 1, wherein said second means comprises a DC restorer circuit for providing said additional bias current.

Claim 5

A circuit according to claim 3, wherein said DC restorer circuit includes a capacitor coupled to said controllable switching means, said controllable switching means conducting in a saturated state during the occurrence of said synchronizing signals.

Claim 6

A circuit according to claim 4, wherein said controllable switching means comprises a first transistor, said first bias current and said additional bias current coupled to a base-emitter junction of said first transistor.

Claim 7

A circuit according to claim 5, wherein said first terminal is coupled to the collector of said first transistor.

Claim 8

A circuit according to claim 5, wherein said source of first reference voltage comprises a second plurality of series coupled diodes through which a third current flows.

Claim 9

A circuit according to claim 1, including noise elimination means comprising third means coupled to said series coupled diodes for generating at a terminal coupled to said third means a third voltage during the occurrence of said synchronizing signals, means for generating a noise reference voltage and disabling means responsive to said third voltage and said noise reference voltage for disabling operation of said sync separator circuit when said third voltage and said noise reference voltage differ by a predetermined value.

Claim 10

A circuit according to claim 8, wherein said third means comprises a resistor through which said additional bias current flows.

Claim 11

A circuit according to claim 8, wherein said disabling means includes switching means coupled to said first plurality of series coupled diodes, and fourth means coupled to said switching means for changing the conduction of said switching means when said third voltage and said noise reference voltage differ by a predetermined value.

Claim 12

A circuit according to claim 9, wherein said fourth means comprises a differential amplifier including second and third differentially coupled transistors, said third voltage and said noise reference voltage coupled, respectively, to first and second input terminals of said differential amplifier.

Claim 13

A circuit according to claim 8, wherein said source of first reference voltage comprises a second plurality of series coupled diodes through which a third current flows.

Claim 14

A circuit according to claim 12, wherein said means for generating a noise reference voltage comprises a first diode coupled in series with said second plurality of series coupled diodes and a voltage divider network coupled across said first diode, said noise reference voltage obtained at a junction point within said voltage divider network.

Claim 15

A sync separator circuit, comprising: a DC restorer circuit responsive to a source of composite video signals, said DC restorer circuit including a controlled semiconductor means; a first impedance coupled to said controlled semiconductor means; biasing means coupled to a control terminal of said controlled semiconductor means for providing a bias current to said controlled semiconductor means, said DC restorer circuit providing an additional current to said control terminal during the occurrence of synchronizing signals within said composite video signals for biasing said controlled semiconductor means into conduction for establishing during said occurrence a first voltage representative of said additional current at a first terminal coupled to said first impedance; a source of reference voltage; and comparator means responsive to said reference voltage and said first voltage for developing an output signal when said first voltage and said reference voltage differ by a predetermined value.

Claim 16

A sync separator circuit, comprising: a DC restorer circuit responsive to a source of composite video signals, said DC restorer circuit including a controlled semiconductor means; a first impedance coupled to said controlled semiconductor means; biasing means coupled to a control terminal of said controlled semiconductor means for providing a bias current to said controlled semiconductor means, said DC restorer circuit providing an additional current to said control terminal during the occurrence of synchronizing signals within said composite video signals for biasing said controlled semiconductor means into conduction for establishing during said occurrence a first voltage representative of said additional current at a first terminal coupled to said first impedance; a source of reference voltage; and comparator means responsive to said reference voltage and said first voltage for developing an output signal when said first voltage and said reference voltage differ by a predetermined value.

Claim 17

A circuit according to claim 14, wherein said DC restorer circuit includes a capacitor for charging to a peak value of said synchronizing signals and a discharging impedance coupled to said capacitor.

Claim 18

A circuit according to claim 15, wherein said controlled semiconductor means comprises a transistor, said biasing means comprising a bias voltage coupled to said discharge impedance, said discharge impedance being coupled to a base-emitter junction of said transistor.

Claim 19

A circuit according to claim 14, including noise elimination means comprising a second terminal coupled to said impedance, a noise component of said additional current establishing a second voltage at said second terminal, and means for disabling operation of said sync separator when said second voltage differs from a noise reference voltage by predetermined values.

Claim 20

A sync separator with noise elimination comprising: an input terminal for coupling thereto a composite video signal; a DC restorer coupled to said input terminal for developing a DC restoration voltage during a sync interval, said DC restorer including a controlled semiconductor; biasing means coupled to a control terminal of said controlled semiconductor for providing a bias voltage to said controlled semiconductor; an impedance coupled to said DC restorer, said DC restoration voltage providing an additional bias voltage to said control terminal for generating a first current through said impedance during said sync interval; a current source coupled to said DC restorer for generating a second current through said impedance during said sync interval, said first and second currents combined developing a first voltage at a first terminal coupled to said impedance; first comparator means with a first comparator input terminal coupled to said first terminal and a second comparator input terminal suitable for coupling to a source of reference voltage for developing a sync signal when said first voltage and said reference voltage differ by a predetermined amount; a second terminal coupled to said impedance; and a second comparator coupled to said second terminal, the magnitude of said DC restoration voltage changing under predetermined noise conditions for changing the voltage at said second terminal for generating at an output terminal of said second comparator a disabling signal for said sync separator.

Claim 21

A sync separator with noise elimination comprising: an input terminal for coupling thereto a composite video signal; a DC restorer coupled to said input terminal for developing a DC restoration voltage during a sync interval, said DC restorer including a controlled semiconductor; biasing means coupled to a control terminal of said controlled semiconductor for providing a bias voltage to said controlled semiconductor; an impedance coupled to said DC restorer, said DC restoration voltage providing an additional bias voltage to said control terminal for generating a first current through said impedance during said sync interval; a current source coupled to said DC restorer for generating a second current through said impedance during said sync interval, said first and second currents combined developing a first voltage at a first terminal coupled to said impedance; first comparator means with a first comparator input terminal coupled to said first terminal and a second comparator input terminal suitable for coupling to a source of reference voltage for developing a sync signal when said first voltage and said reference voltage differ by a predetermined amount; a second terminal coupled to said impedance; and a second comparator coupled to said second terminal, the magnitude of said DC restoration voltage changing under predetermined noise conditions for changing the voltage at said second terminal for generating at an output terminal of said second comparator a disabling signal for said sync separator.