Horizontal sync detector

Claim 1

An improved horizontal sync detector circuit for use in high resolution digital processing of a video data signal which comprises: negative peak detector circuit means for having sensitivity only to the negative peaks of said video data signal, which stores a voltage potential representing the largest signal value of said video data signal it received, and for allowing a reference point to be established despite changes in video data signal values and changes caused by range in ambient temperatures; said negative peak detector means comprising: a first stage operational amplifier (Z 1 ); a first scaling resistor (R 1 ) having a first end electrically connected to said video signal and another end coupled to the negative input terminal of said amplifier (Z 1 ); a biasing resistor (R 3 ) which electrically couples the positive input of said first emplifier (Z 1 ) to ground connection means; a first diode (D 1 ), having its anode terminal electrically connected as a shunt, at the negative terminal of said first amplifier (Z 1 ) and the said first diode's cathode terminal electrically coupled to the output of said first amplifier (Z 1 ), said first diode (D 1 ) preventing said first amplifier (Z 1 ) from saturating in a negative direction; a second diode (D 2 ) having an anode terminal electrically connected to the junction of the output of said first amplifier (Z 1 ) and the cathode terminal of said first diode (D 1 ); a storage capacitor (C 1 ) electrically coupled between a cathode terminal of said second diode (D 2 ) and ground, said second diode (D 2 ) allowing said capacitor (C 1 ) to be driven in one direction only; a second stage operational amplifier (Z 2 ) having a positive terminal electrically connected to a common junction between said capacitor (C 1 ) and said cathode terminal of said second diode (D 2 ), and a negative input terminal; and a second scaling resistor (R 2 ) having one end electrically connected to the negative input terminal of said second amplifier (Z 2 ) and to the output of said second amplifier (Z 2 ), and the other end to the negative input terminal of said first amplifier (Z 1 ), said first and second scaling resistors completing the feedback paths around said first and second amplifiers (Z 1 ) and (Z 2 ) respectively, for determining the throughput gain; proportioning amplifier circuit means having input means electrically coupled to the output of said peak detector means for setting a triggering point at a specified point above the negative peaks of a horizontal sync pulse, and for constantly adjusting said triggering point of said detector means to be dependent upon the signal level of said video data signal and proximate to the center level of said horizontal sync pulse; and comparator circuit means electrically coupled to the output of said proportioning amplifier means and the input video data signal for stripping away the video data signal and converting the video sync information thereof to a TTL logic level.