US3869624A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Peak holding circuit for extremely narrow pulses
Assignee: National Aeronautics and Space Administration
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Filing: 1973-05-21
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Granted: 1975-03-04
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Expires: 1993-05-21
Abstract
Abstract An improved pulse stretching circuit comprising: a high speed wide-band amplifier connected in a fast charge integrator configuration; a holding circuit including a capacitor connected in parallel with a discharging network which employs a resistor and an FET; and an output buffer amplifier. Input pulses of very short duration are applied to the integrator charging the capacitor to a value proportional to the input pulse amplitude. After a predetermined period of time, conventional circuitry generates a ''''dump pulse'''' which is applied to the gate of the FET making a low resistance path to ground which discharges the capacitor. When the dump pulse terminates, the circuit is ready to accept another pulse to be stretched. The very short input pulses are thus stretched in width so that they may be analyzed by conventional pulse height analyzers.
Inventors
- 👤 James C Administrator Fletcher
- 👤 Robert W O'neill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 11:31
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/04; G; G01; G01R; G01R19/00; G01R19/04
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
154 words
A circuit for lengthening the time duration of an electrical pulse comprising: a. first input amplifying means; b. an integrating feedback loop connected between the output and one input of said amplifying means for frequency control; c. coupling means connecting the output of said first amplifying means with one input of a second amplifying means; d. compensating means included in said integrating feedback loop for compensating for nonlinear characteristics in said coupling means; e. pulse width control means having an input supplied with said electrical pulse and an output applied to said second amplifying means for regulating the width of pulses output from said second amplifying means; and f. threshold discriminating means included in said pulse width control means for determining the presence of an electrical pulse having predetermined electrical characteristics at the Input to said first amplifying means whereby only pulses having such predetermined characteristics have their widths regulated by said control means.
Claim 2
Dependent Claim
154 words
A circuit for lengthening the time duration of an electrical pulse comprising: a. first input amplifying means; b. an integrating feedback loop connected between the output and one input of said amplifying means for frequency control; c. coupling means connecting the output of said first amplifying means with one input of a second amplifying means; d. compensating means included in said integrating feedback loop for compensating for nonlinear characteristics in said coupling means; e. pulse width control means having an input supplied with said electrical pulse and an output applied to said second amplifying means for regulating the width of pulses output from said second amplifying means; and f. threshold discriminating means included in said pulse width control means for determining the presence of an electrical pulse having predetermined electrical characteristics at the Input to said first amplifying means whereby only pulses having such predetermined characteristics have their widths regulated by said control means.
Claim 3
Dependent Claim
81 words
A circuit as defined in claim 1 wherein: a. said first input amplifying means includes a differential input operational amplifier; b. said feedback loop includes a first leg having a parallel RC circuit connected in series with a first diode and a second leg, in parallel with the first leg and including a second diode; and c. the anode of said first diode and the cathode of said second diode are connected to the inverting input of said first amplifying means.
Claim 4
Dependent Claim
85 words
A circuit as defined in claim 2 wherein: a. said second amplifying means includes an operational amplifier connected in the unity gain configuration; b. said coupling means includes a diode having its cathode connected to the output of said first amplifying means; c. said pulse width control means includes a holding circuit formed by a charging capacitor connected in parallel with an FET controlled discharge circuit; and d. the output of said holding circuit is connected to the non-inverting input of said second amplifying means.
Claim 5
Dependent Claim
36 words
A circuit as defined in claim 3 wherein the output of said threshold discriminating means is connected to the gate of said FET for generating a dump pulse to discharge the charge on said charging capacitor.
Claim 6
Dependent Claim
22 words
A circuit as defined in claim 1 wherein the output of said second amplifying means is fedback to said first amplifying means.
Claim 7
Dependent Claim
81 words
A circuit as defined in claim 5 wherein: a. said first input amplifying means includes a differential input operational amplifier; b. said feedback loop includes a first leg having a parallel RC circuit connected in series with a first diode and a second leg, in parallel with the first leg and including a second diode; and c. the anode of said first diode and the cathode of said second diode are connected to the inverting input of said first amplifying means.
Claim 8
Dependent Claim
85 words
A circuit as defined in claim 6 wherein: a. said second amplifying means includes an operational amplifier connected in the unity gain configuration; b. said coupling means includes a diode having its cathode connected to the output of said first amplifying means; c. said pulse width control means includes a holding circuit formed by a charging capacitor connected in parallel with an FET controlled discharge circuit; and d. the output of said holding circuit is connected to the non-inverting input of said second amplifying means.
Claim 9
Dependent Claim
36 words
A circuit as defined in claim 7 wherein the output of said threshold discriminating means is connected to the gate of said FET for generating a dump pulse to discharge the charge on said charging capacitor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-03-03 | 1978-09-02 | 1979-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-03-03 | 1982-09-02 | 1983-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-03-03 | 1986-09-02 | 1987-03-04 | $7700.00 | Window Closed / Lapsed |