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US4516042A Expired / Lapsed US ⏱️ 0.0 years remaining

Clamp circuits

Assignee: Tektronix Inc
•
Filing: 1982-06-30
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Granted: 1985-05-07
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Expires: 2002-06-30
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Abstract

Abstract A circuit for providing a signal which is clamped to a desired DC voltage level comprises an amplifier for receiving an input signal and a feedback loop for developing an offset signal for combination with the input signal by the amplifier to provide an output signal at the desired DC voltage level. The feedback loop includes a noise detector for detecting the level of noise present in the output signal, and adjusting the time constant of the feedback loop in dependence thereon.

Inventors

  • 👤 Michael D. Nakamura

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 19:04
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/16; H04N5/18; H04N5/185; H04N5/21; H04N5/213

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 201 words
A circuit for providing a signal which is clamped to a desired DC voltage level, comprising: amplifier means for receiving an input signal; means for developing an offset signal for combination with the input signal by the amplifier means to provide an output signal at the desired DC voltage level, the signal developing means having a variable time constant and operating, in use, to bring the output signal to the desired DC voltage level in an interval dependent upon the value of said time constant; a noise detector which is operative, in use, to generate a first control signal representative of the deviation between the actual average absolute value of the output signal voltage during a predetermined interval and a predetermined nominal average absolute value of the output signal voltage during said interval, the signal developing means being responsive to the first control signal to adjust the time constant of the signal developing means; means for providing a second control signal if the actual DC voltage level of the output signal during said interval exceeds a predetermined threshold value; and means for responding to said second control signal by inhibiting application of the first control signal to the signal developing means.
Claim 2
Dependent Claim 201 words
A circuit for providing a signal which is clamped to a desired DC voltage level, comprising: amplifier means for receiving an input signal; means for developing an offset signal for combination with the input signal by the amplifier means to provide an output signal at the desired DC voltage level, the signal developing means having a variable time constant and operating, in use, to bring the output signal to the desired DC voltage level in an interval dependent upon the value of said time constant; a noise detector which is operative, in use, to generate a first control signal representative of the deviation between the actual average absolute value of the output signal voltage during a predetermined interval and a predetermined nominal average absolute value of the output signal voltage during said interval, the signal developing means being responsive to the first control signal to adjust the time constant of the signal developing means; means for providing a second control signal if the actual DC voltage level of the output signal during said interval exceeds a predetermined threshold value; and means for responding to said second control signal by inhibiting application of the first control signal to the signal developing means.
Claim 3
Dependent Claim 55 words
A circuit according to claim 1, wherein said signal developing means comprise means for identifying a portion of the output signal having a nominally constant DC voltage level and for providing a signal which is dependent upon the actual DC voltage level of said portion of the output signal and which constitutes said offset signal.
Claim 4
Dependent Claim 39 words
A circuit according to claim 2, wherein said predetermined interval over which the actual absolute value of the output signal voltage is averaged in order to generate the first control signal corresponds to said portion of the output signal.
Claim 5
Dependent Claim 74 words
A circuit according to claim 1, wherein the noise detector has an input terminal to which a signal corresponding to said output signal is applied during said predetermined interval, a converter having an output terminal at which said first control signal is developed, and switch means interposed between said input terminal and said converter and responsive to said second control signal to prevent the signal applied to the input terminal from reaching said converter.
Claim 6
Dependent Claim 30 words
A circuit according to claim 4, wherein the output signal has a nominally constant DC voltage level during said predetermined interval, and said converter is a root mean square converter.
Claim 7
Dependent Claim 92 words
A circuit according to claim 4, wherein the switch means comprise a first switch and a second switch connected in parallel between said input terminal and said converter, the first switch being normally open and the second switch being normally closed and being responsive to the second control signal to open for a predetermined interval, and said switch means also comprising an override circuit for detecting whether the frequency with which the second control signal is generated exceeds a predetermined limit and closing said first switch if said frequency exceeds said limit.
Claim 8
Dependent Claim 86 words
A circuit according to claim 1, wherein said signal developing means comprise means for identifying a portion of the output signal having a nominally constant DC voltage level and for providing a signal which is dependent upon the actual DC voltage level of said portion of the output signal and which constitutes said offset signal, and the first control signal represents the deviation between the actual average absolute value of the voltage level of said portion of the output signal said nominally constant DC voltage level.

References Cited (Backward Citations)

GB902475A Cited
US3549801A Cited
US3560648A Cited
US4415929A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-05-06 1988-11-05 1989-05-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-05-06 1992-11-05 1993-05-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-05-06 1996-11-05 1997-05-07 $7700.00 Window Closed / Lapsed

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