Patent US4660165A successfully refreshed from Google Patents.
US4660165A
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Pyramid carry adder circuit
Assignee: Raytheon Co
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Filing: 1984-04-03
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Granted: 1987-04-21
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Expires: 2004-04-03
Abstract
Abstract A digital adder circuit using principles similar to a pyramid carry adder, but with the ability to assimilate intermediate carry bits more rapidly. The circuit includes at least one adder stage for receiving multiple intermediate sum bits and multiple intermediate carry bits as inputs, and reducing the number of carry bits by a factor of at least three. The adder stage as disclosed is implemented in the form of current-mode logic. Preferably, a first adder stage includes multiple two-bit adder circuits, also in the form of current-mode logic, each two-bit adder circuit producing as outputs two sum bits and a carry bit.
Inventors
- 👤 Rodney T. Masumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:28
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/506; G06F7/508; G06F2207/00; G06F2207/38; G06F2207/48; G06F2207/4802; G06F2207/4806
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
185 words
An adder circuit with high-speed carry assimilation capability, said circuit comprising: a first adder stage, including means for processing two multi-bit numbers to be added together, and producing an intermediate multi-bit sum output and a multi-bit carry output; at least one additional adder stage, including means for logically combining sum outputs and carry outputs from said first stage, to produce carry and sum output bits such that the number of carry bits is reduced by a factor of at least three; means for coupling the intermediate carry output bits and the intermediate sum output bits from said first adder stage to said additional adder stage; wherein said first adder stage includes a plurality of two-bit adder modules, each of which produces a two-bit intermediate sum output and a single carry output bit; and wherein said additional adder stage is a second stage, and includes a plurality of second-stage adder modules, each of which receives the carry outputs of at least three of said two-bit adders in said first adder stage, and produces as outputs a set of intermediate sum bits and a single carry bit.
Claim 2
Dependent Claim
185 words
An adder circuit with high-speed carry assimilation capability, said circuit comprising: a first adder stage, including means for processing two multi-bit numbers to be added together, and producing an intermediate multi-bit sum output and a multi-bit carry output; at least one additional adder stage, including means for logically combining sum outputs and carry outputs from said first stage, to produce carry and sum output bits such that the number of carry bits is reduced by a factor of at least three; means for coupling the intermediate carry output bits and the intermediate sum output bits from said first adder stage to said additional adder stage; wherein said first adder stage includes a plurality of two-bit adder modules, each of which produces a two-bit intermediate sum output and a single carry output bit; and wherein said additional adder stage is a second stage, and includes a plurality of second-stage adder modules, each of which receives the carry outputs of at least three of said two-bit adders in said first adder stage, and produces as outputs a set of intermediate sum bits and a single carry bit.
Claim 3
Dependent Claim
32 words
An adder circuit as set forth in claim 1, wherein: said first and second adder stages are implemented in current-mode logic, to provide a reduced processing delay at each of said stages.
Claim 4
Dependent Claim
35 words
An adder circuit as set forth in claim 1, wherein: said second adder stage receives four sum input bits and three intermediate carry bits, and produces four sum output bits and one carry output bit.
Claim 5
Dependent Claim
124 words
A high-speed adder circuit, comprising: a first adder stage for processing two multi-bit numbers to be added together, said first adder stage including a plurality of two-bit adder modules, each of which produces a two-bit sum output and a single carry bit output; at least one additional adder stage including a plurality of second-stage adder modules, each of which includes means for processing n carry bits and 2(n-1) sum bits output by said two-bit adder modules, where n is at least three, and means for logically combining the sum and carry inputs to produce one carry output and 2(n-1) sum outputs; and means for coupling the carry output bits and the sum output bits from said first adder stage to said additional adder stage.
Claim 6
Dependent Claim
124 words
A high-speed adder circuit, comprising: a first adder stage for processing two multi-bit numbers to be added together, said first adder stage including a plurality of two-bit adder modules, each of which produces a two-bit sum output and a single carry bit output; at least one additional adder stage including a plurality of second-stage adder modules, each of which includes means for processing n carry bits and 2(n-1) sum bits output by said two-bit adder modules, where n is at least three, and means for logically combining the sum and carry inputs to produce one carry output and 2(n-1) sum outputs; and means for coupling the carry output bits and the sum output bits from said first adder stage to said additional adder stage.
Claim 7
Dependent Claim
75 words
A high-speed adder circuit as set forth in claim 4, wherein said means for logically combining the sum and carry inputs includes: a first set of parallel current-mode logic circuits, for generating from the sum and carry input signals a plurality of intermediate carry signals; and a second set of parallel current-mode logic circuits, for generating the sum output signals and the carry output signal from the sum input signals and the intermediate carry signals.
Claim 8
Dependent Claim
39 words
A high-speed adder circuit as set forth in claim 5, wherein: each of the two-bit adder modules in said first adder stage includes a current-mode logic circuit for generating a two-bit sum output and a single carry bit output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-04-20 | 1990-10-20 | 1991-04-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-04-20 | 1994-10-20 | 1995-04-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-04-20 | 1998-10-20 | 1999-04-21 | $7700.00 | Window Closed / Lapsed |