US3566098A
Expired / Lapsed
US
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High speed adder circuit
Assignee: NEC Corp
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Filing: 1967-09-26
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Granted: 1971-02-23
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Expires: 1987-09-26
Abstract
Abstract A high-speed parallel adder circuit employing wired AND CML circuitry in which the digits corresponding to digit positions of the two multibit words are added to obtain an initial position sum and an initial position carry. Selected digit positions are divided into groups to develop group sum and group carry signals for each of said groups. The groups, in turn, are divided into super groups, and the group sum and carry signals, in turn, are employed to develop super group sum and super group carry signals. The super group sum and super group carry signals are, in turn, utilized to develop a real super group carry for each super group and to develop, indirectly, a real carry for each group. The real group carry signals, in turn, are employed for the development of a propagated carry signal for each digit position of each group which is developed by real group carry signals transferred to a selected digit position within each of said groups. Simultaneously, therewith, the initial position sum and initial position carry signals of each digit position are employed for the purpose of developing a modified position sum signal within a group of digits of which the modified position sum signal is combined with the intergroup position carry signal which is propagated from the adjacent lower group to generate a signal representing the final position sum. Hereafter, all of the initial positions sum, group sum, supergroup sum, modified position sum, real group carry, real supergroup carry, intergroup position carry, final position sum or the like, may be abbreviated respectively as sum or carry signals when their meaning is clear in their related contex. The high-speed parallel adder circuit of the invention is capable of performing all of the above functions through the employment of circuitry which requires only seven logical levels.
Inventors
- 👤 Makoto Kono
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 01:06
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/506; G06F7/508; G06F2207/00; G06F2207/38; G06F2207/48; G06F2207/4802; G06F2207/4806
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
219 words
A high-speed parallel-type adder circuit for adding two multibit binary numbers comprising: a plurality of first half-adder circuit means associated with each digit position for adding binary inputs associated with each digit position to generate an initial position sum and an initial position carry signal; a plurality of second circuit means each being coupled to different groups of said first half-adder circuits for generatinG a group carry and group sum signal; a plurality of third circuit means coupled to associated second circuit means for generating a real group carry signal; a plurality of fourth circuit means each coupled to an associated half-adder circuit means and an associated one of sad third circuit means for generating an intergroup position carry signal from the adjacent lower order group; a plurality of fifth circuit means each coupled to said halfadder circuits associated with a different group of said digit positions for generating an intragroup carry signal; a plurality of sixth circuit means each coupled to an associated one of said fifth circuit means and an associated one of said half-adder circuits for generating a modified position sum signal; and a plurality of seventh circuit means each coupled to an associated one of said sixth circuit means and an associated one of said fourth circuit means for generating a final position sum signal.
Claim 2
Dependent Claim
219 words
A high-speed parallel-type adder circuit for adding two multibit binary numbers comprising: a plurality of first half-adder circuit means associated with each digit position for adding binary inputs associated with each digit position to generate an initial position sum and an initial position carry signal; a plurality of second circuit means each being coupled to different groups of said first half-adder circuits for generatinG a group carry and group sum signal; a plurality of third circuit means coupled to associated second circuit means for generating a real group carry signal; a plurality of fourth circuit means each coupled to an associated half-adder circuit means and an associated one of sad third circuit means for generating an intergroup position carry signal from the adjacent lower order group; a plurality of fifth circuit means each coupled to said halfadder circuits associated with a different group of said digit positions for generating an intragroup carry signal; a plurality of sixth circuit means each coupled to an associated one of said fifth circuit means and an associated one of said half-adder circuits for generating a modified position sum signal; and a plurality of seventh circuit means each coupled to an associated one of said sixth circuit means and an associated one of said fourth circuit means for generating a final position sum signal.
Claim 3
Dependent Claim
89 words
The high-speed parallel-type adder circuit for adding two multibit binary numbers as claimed in claim 1 further comprising: a a plurality of eighth circuit means each coupled to an associated one of said second circuit means for generating a supergroup carry signal and a supergroup sum signal; and a plurality of ninth circuit means each coupled between associated ones of said eighth circuit means and said third circuit means for generating a real supergroup carry signal employed by said third circuit means to generate said real group carry signal.
Claim 4
Dependent Claim
310 words
A high-speed parallel-type adder circuit for adding two multibit binary numbers comprising: a plurality of first half-adder circuit means associated with each digit position for adding binary inputs associated with each digit position to generate an initial position sum and initial position carry signal; a plurality of second circuit means each being coupled to different groups of said first half-adder circuit means for generating a complementary group carry signal and a true group sum signal; a plurality of third circuit means each coupled to said second circuit means for generating a true supergroup carry and a true supergroup sum signal; a plurality of fourth circuit means each coupled to said third circuit means for generating a real supergroup carry signal which is to be a complementary signal as against the true signals produced by the said third circuit means; a plurality of fifth circuit means each coupled to both of said second circuit and said fourth circuit mans for generating a real group carry signal which is a true signal as against the complementary signals produced respectively by said fourth circuit means and said second circuit means; a plurality of sixth circuit means each coupled to selected ones of both of said first half-adder circuit means and said fifth circuit means for generating an intergroup position carry signal from the adjacent lower order group; a plurality of seventh circuit means each coupled to selected ones of said first half-adder circuit means associated with a different group of said digital positions for generating an intragroup carry signal; a plurality of eighth circuit means each coupled to both of said seventh circuit means and said half-adder circuit means for generating a modified sum signal; and a plurality of ninth circuit means each coupled to both of said sixth circuit means and said eight circuit means for generating a final position sum signal.
Claim 5
Dependent Claim
310 words
A high-speed parallel-type adder circuit for adding two multibit binary numbers comprising: a plurality of first half-adder circuit means associated with each digit position for adding binary inputs associated with each digit position to generate an initial position sum and initial position carry signal; a plurality of second circuit means each being coupled to different groups of said first half-adder circuit means for generating a complementary group carry signal and a true group sum signal; a plurality of third circuit means each coupled to said second circuit means for generating a true supergroup carry and a true supergroup sum signal; a plurality of fourth circuit means each coupled to said third circuit means for generating a real supergroup carry signal which is to be a complementary signal as against the true signals produced by the said third circuit means; a plurality of fifth circuit means each coupled to both of said second circuit and said fourth circuit mans for generating a real group carry signal which is a true signal as against the complementary signals produced respectively by said fourth circuit means and said second circuit means; a plurality of sixth circuit means each coupled to selected ones of both of said first half-adder circuit means and said fifth circuit means for generating an intergroup position carry signal from the adjacent lower order group; a plurality of seventh circuit means each coupled to selected ones of said first half-adder circuit means associated with a different group of said digital positions for generating an intragroup carry signal; a plurality of eighth circuit means each coupled to both of said seventh circuit means and said half-adder circuit means for generating a modified sum signal; and a plurality of ninth circuit means each coupled to both of said sixth circuit means and said eight circuit means for generating a final position sum signal.
References Cited (Backward Citations)
US3440412A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-22 | 1974-08-24 | 1975-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-22 | 1978-08-24 | 1979-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-22 | 1982-08-24 | 1983-02-23 | $7700.00 | Window Closed / Lapsed |