US3697735A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-speed parallel binary adder
Assignee: Unisys Corp
•
Filing: 1969-07-22
•
Granted: 1972-10-10
•
Expires: 1989-07-22
Abstract
Abstract There is described a parallel adder for operands of 48 bits in which the carry information is generated simultaneously for all orders. The carry logic, consisting entirely of AND gates, is arranged in three levels. The adder consists of independent subadders of four orders each. The carry logic and subadders combine to form a maximum of four cascaded gate levels for generating the sum of any order of bits. Duplicate true and false logic is used at all levels. The second and third levels of the carry logic are arranged in an interleaved configuration to limit fanning.
Inventors
- 👤 Lawrence G Hanson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:40
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/506; G06F7/508
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
327 words
A high-speed parallel binary adder comprising first and second input registers for storing a large number of binary bits representing an augend and an addend, an output register for storing a resultant, a gating logic circuit consisting entirely and exclusively of gating elements interconnecting the two input registers and the output register for producing the binary sum in the output register of the binary numbers in the two input registers, the gating circuit including an adder logic section and a carry logic section, both sections being connected to the outputs of the two input registers, the output of the carry section being connected to the adder section, the adder section including a plurality of identical sub-adder units, each of the sub-adder units receiving a portion of the bits from the two input registers and receiving a carry bit from the carry section, the carry section including three levels of gating elements, the first level having a plurality of identical sections, each section receiving two bits from each of the input registers and providing two binary output signals, the second level having a plurality of identical sections, all but the highest order and lowest order sections receiving the output signals from four sections of the first level with each section having two inputs common with two inputs to one other section and having the remaining two inputs common with two inputs to another section and providing two binary output signals, and the third level having two identical sections, one section receiving all the output signals from a first group of sections of the second level and the other section receiving all the output signals of the remaining group of sections of the second level, the sections in each of said groups of the second level having no inputs in common with other sections of the same group, each section of the third level providing a plurality of output carry bits, each subadder receiving one of said carry bits.
Claim 2
Dependent Claim
327 words
A high-speed parallel binary adder comprising first and second input registers for storing a large number of binary bits representing an augend and an addend, an output register for storing a resultant, a gating logic circuit consisting entirely and exclusively of gating elements interconnecting the two input registers and the output register for producing the binary sum in the output register of the binary numbers in the two input registers, the gating circuit including an adder logic section and a carry logic section, both sections being connected to the outputs of the two input registers, the output of the carry section being connected to the adder section, the adder section including a plurality of identical sub-adder units, each of the sub-adder units receiving a portion of the bits from the two input registers and receiving a carry bit from the carry section, the carry section including three levels of gating elements, the first level having a plurality of identical sections, each section receiving two bits from each of the input registers and providing two binary output signals, the second level having a plurality of identical sections, all but the highest order and lowest order sections receiving the output signals from four sections of the first level with each section having two inputs common with two inputs to one other section and having the remaining two inputs common with two inputs to another section and providing two binary output signals, and the third level having two identical sections, one section receiving all the output signals from a first group of sections of the second level and the other section receiving all the output signals of the remaining group of sections of the second level, the sections in each of said groups of the second level having no inputs in common with other sections of the same group, each section of the third level providing a plurality of output carry bits, each subadder receiving one of said carry bits.
Claim 3
Dependent Claim
48 words
Apparatus as defined in claim 1 wherein each subadder receives four binary bits from each of the input registers and generates four output bits representing the binary sum of said four input bits and the carry bit from the third level of gating elements in said carry section.
Claim 4
Dependent Claim
36 words
Apparatus as defined in claim 2 wherein each identical section of all three gating levels includes duplicate gating for both true and false logic to provide both a carry bit and its complement to each subadder.
Claim 5
Dependent Claim
260 words
Apparatus as defined in claim 1 wherein each section of the first gating level includes gating logic for providing said two output signals in accordance with the equations R1m AA2m.BB2m+AA2m 1.BB2m 1.(AA2m+BB2m) M1m (AA2m+BB2m).(AA2m 1+BB2m 1) where R1 and M1 are the two output signals, AA and BB are bits from the two input registers with the order of the bits represented by the subscripts, m is the order of the section and is any integer starting with 1, the dot (.) represents the logical AND, and the plus (+) represents the logical inclusive OR; each section of the second gating level includes gating logic for providing said two output signals in accordance with the equations R2n R12n 3.M12n 2.M12n 1.M12n +R12n 2.M12n 1.M12n +R12n 1.M12n +R12n M2n M12n 3.M12n 2.M12n 1.M12n where M2 and R2 are the two output signals and n is the order of the section and is any integer starting with 1; and each section of the third gating level includes gating logic for providing said plurality of carry bIts in accordance with the following series of equations: Cp R2p Cp 2 R2p.M2p 2+R2p 2 Cp 4 R2p.M2p 2.M2p 4+R2p 2.M2p 4+R2p 4 . . . Cp q R2p.M2p 2.M2p 4 . . . M2p q+R2p 2. M2p 4 . . . M2p q+ . . . +R2p q where C is an output carry bit, p is either 0 or 1 and q is any even integer, and the subscript of C represents the order of the subadder to which the carry bit is connected.
Claim 6
Dependent Claim
310 words
A high-speed parallel binary adder for adding two binary coded operands and generating the binary sum comprising a carry generating circuit receiving simultaneously all orders of bits of both the operands and generating simultaneously a plurality of output signals, and a plurality of identical sub-adder circuits, each sub-adder circuit receiving a proportionate share of the bits of the two operands and one of said output signals from the carry generating circuit, each subadder generating the same proportionate share of the bits of the binary sum of said operands, each of said sub-adder circuits including, for each bit of the two operands received, a first exclusive OR circuit having two inputs to which the two operand bits are applied and an output, and a second exclusive OR circuit having two inputs, one input of said second exclusive OR circuit being connected to the output of the first exclusive OR circuit, the other input of the second exclusive OR circuit being connected to said one of the output signals from the carry generating circuit, and, for all but the lowest order bit of the two operands received by the sub-adder, a third exclusive OR circuit, the output of the second and third exclusive OR circuits being connected to a common output providing one bit of the sum, the third exclusive OR circuit having one input connected to the output of the first exclusive OR circuit, an internal carry logic circuit connected to all the lower order input bits applied to the sub-adder, the logic circuit having an output connected to the other input of the third exclusive OR circuit, and means for controlling the output of the first exclusive OR circuit such that the output is true only if all the outputs of the corresponding first exclusive OR circuits associated with the lower order bits applied to the same sub-adder are true.
Claim 7
Dependent Claim
310 words
A high-speed parallel binary adder for adding two binary coded operands and generating the binary sum comprising a carry generating circuit receiving simultaneously all orders of bits of both the operands and generating simultaneously a plurality of output signals, and a plurality of identical sub-adder circuits, each sub-adder circuit receiving a proportionate share of the bits of the two operands and one of said output signals from the carry generating circuit, each subadder generating the same proportionate share of the bits of the binary sum of said operands, each of said sub-adder circuits including, for each bit of the two operands received, a first exclusive OR circuit having two inputs to which the two operand bits are applied and an output, and a second exclusive OR circuit having two inputs, one input of said second exclusive OR circuit being connected to the output of the first exclusive OR circuit, the other input of the second exclusive OR circuit being connected to said one of the output signals from the carry generating circuit, and, for all but the lowest order bit of the two operands received by the sub-adder, a third exclusive OR circuit, the output of the second and third exclusive OR circuits being connected to a common output providing one bit of the sum, the third exclusive OR circuit having one input connected to the output of the first exclusive OR circuit, an internal carry logic circuit connected to all the lower order input bits applied to the sub-adder, the logic circuit having an output connected to the other input of the third exclusive OR circuit, and means for controlling the output of the first exclusive OR circuit such that the output is true only if all the outputs of the corresponding first exclusive OR circuits associated with the lower order bits applied to the same sub-adder are true.
Claim 8
Dependent Claim
46 words
Apparatus as defined in claim 5 wherein said internal carry logic circuit provides a binary output that is defined by the relation: An.Bn+An 1.Bn 1(An+Bn)+An 2.Bn 2(An 1+Bn 1)(An+Bn)+ . . . where An and Bn are the next lower order input bits to the sub-adder.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-10 | 1976-04-10 | 1976-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-10 | 1980-04-10 | 1980-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-10 | 1984-04-10 | 1984-10-10 | $7700.00 | Window Closed / Lapsed |