Patent US4658161A successfully refreshed from Google Patents.
US4658161A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Split phase loop
Assignee: Avago Technologies International Sales Pte Ltd
•
Filing: 1985-08-13
•
Granted: 1987-04-14
•
Expires: 2005-08-13
Abstract
Abstract An apparatus and method are described for generating a plurality of clock edges from a reference clock signal. The clock edges which are generated are locked in phase with the reference clock signal. The edges may be at any integral or non-integral multiple of the reference clock frequency.
Inventors
- 👤 John R. Spencer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 08:26
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/15026; H03K5/1504
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
263 words
An apparatus for generating a clock edge referenced to a clock, the apparatus comprising: first variable delay means having an input line to carry an input signal, an output line to carry an output signal and a control line to carry a control signal for delaying the input signal by a first delay interval to generate the output signal, the output signal being the clock edge, the input line connected to the clock, the first delay interval responsive to the control signal; second variable delay means having an input line to carry an input signal, an output line to carry an output signal and a control line to carry a control signal for delaying the input signal by a second delay interval to generate the output signal, the input line connected to the output line of the first variable delay means, the second delay interval responsive to the control signal; and comparator means having a first and second input line to carry a first and second signal and an output line to carry a control signal for comparing the first signal to the second signal and generating the control signal, the first input line connected to the clock, the second input line connected to the output line of the second variable delay means, the output line connected to the control line of the first and second variable delay means for increasing the first and second delay intervals if the second signal occurs before the first signal or decreasing the first and second delay intervals if the first signal occurs before the second signal.
Claim 2
Independent Claim
263 words
An apparatus for generating a clock edge referenced to a clock, the apparatus comprising: first variable delay means having an input line to carry an input signal, an output line to carry an output signal and a control line to carry a control signal for delaying the input signal by a first delay interval to generate the output signal, the output signal being the clock edge, the input line connected to the clock, the first delay interval responsive to the control signal; second variable delay means having an input line to carry an input signal, an output line to carry an output signal and a control line to carry a control signal for delaying the input signal by a second delay interval to generate the output signal, the input line connected to the output line of the first variable delay means, the second delay interval responsive to the control signal; and comparator means having a first and second input line to carry a first and second signal and an output line to carry a control signal for comparing the first signal to the second signal and generating the control signal, the first input line connected to the clock, the second input line connected to the output line of the second variable delay means, the output line connected to the control line of the first and second variable delay means for increasing the first and second delay intervals if the second signal occurs before the first signal or decreasing the first and second delay intervals if the first signal occurs before the second signal.
Claim 3
Dependent Claim
98 words
An apparatus as in claim 1 for generating a second clock edge further comprising: third variable delay means having an input line to carry an input signal, an output line to carry an output signal and a control line to carry a control signal for delaying the input signal by a third delay interval to generate the output signal, the output signal being the second generated clock edge, the input line connected to the clock, the third delay interval responsive to the control signal, the output line connected to the input line of the first variable delay means.
Claim 4
Dependent Claim
18 words
An apparatus as in claim 1 wherein the first delay interval is equal to the second delay interval.
Claim 5
Dependent Claim
84 words
An apparatus as in claim 1 for generating high current clock edges further comprising: third variable delay means having an input line to carry an input signal, an output line to carry an output signal and a control line to carry a control signal for delaying the input signal by the first delay interval to generate the output signal, the input line connected to the clock, the first delay interval responsive to the control signal, the output signal being the high current clock edge.
Claim 6
Independent Claim
86 words
A method for generating a clock edge referenced to a clock signal, the apparatus comprising: delaying the clock signal in proportion to a control signal to generate a first signal and the clock edge; delaying the first signal in proportion to a control signal to generate a second signal; comparing the second signal to the clock signal; and adjusting the control signal to increase the delay if the second signal leads the clock signal or decrease the delay if the second signal lags the clock signal.
Claim 7
Independent Claim
86 words
A method for generating a clock edge referenced to a clock signal, the apparatus comprising: delaying the clock signal in proportion to a control signal to generate a first signal and the clock edge; delaying the first signal in proportion to a control signal to generate a second signal; comparing the second signal to the clock signal; and adjusting the control signal to increase the delay if the second signal leads the clock signal or decrease the delay if the second signal lags the clock signal.
Claim 8
Dependent Claim
48 words
A method as in claim 5 for generating additional clock edges further comprising: delaying the second signal in proportion to a control signal to generate a third signal and supplying the third signal in place of the second signal to the step of comparing and step of adjusting.
Claim 9
Independent Claim
267 words
An apparatus for generating a clock edge referenced to a clock and alternate clock, the apparatus comprising: first variable delay means having an input line to carry an input signal, an output line to carry an output signal and a control line to carry a control signal for delaying the input signal by a first delay interval to generate the output signal, the output signal being the clock edge, the input line connected to the clock, the first delay interval responsive to the control signal; second variable delay means having an input line to carry an input signal, an output line to carry an output signal and a control line to carry a control signal for delaying the input signal by a second delay interval to generate the output signal, the input line conneced to the output line of the first variable delay means, the second delay interval responsive to the control signal; and comparator means having a first and second input line to carry a first and second signal and an output line to carry a control signal for comparing the first signal to the second signal and generating the control signal, the first input line connected to the alternate clock, the second input line connected to the output line of the second variable delay means, the control signal connected to the control line of the first and second variable delay means for increasing the first and second delay interval if the second signal occurs before the first signal or decreasing the first and second delay interval if the first signal occurs before the second signal.
Claim 10
Independent Claim
267 words
An apparatus for generating a clock edge referenced to a clock and alternate clock, the apparatus comprising: first variable delay means having an input line to carry an input signal, an output line to carry an output signal and a control line to carry a control signal for delaying the input signal by a first delay interval to generate the output signal, the output signal being the clock edge, the input line connected to the clock, the first delay interval responsive to the control signal; second variable delay means having an input line to carry an input signal, an output line to carry an output signal and a control line to carry a control signal for delaying the input signal by a second delay interval to generate the output signal, the input line conneced to the output line of the first variable delay means, the second delay interval responsive to the control signal; and comparator means having a first and second input line to carry a first and second signal and an output line to carry a control signal for comparing the first signal to the second signal and generating the control signal, the first input line connected to the alternate clock, the second input line connected to the output line of the second variable delay means, the control signal connected to the control line of the first and second variable delay means for increasing the first and second delay interval if the second signal occurs before the first signal or decreasing the first and second delay interval if the first signal occurs before the second signal.
Claim 11
Dependent Claim
100 words
An apparatus as in claim 7 wherein the comparator means further comprises: a flag generating means for comparing the first signal to the second signal and generating a first flag if the rising edge of the first signal leads the rising edge of the second signal, a second flag if the rising edge of the first signal lags the rising edge of the second signal, and a third flag if the rising edge occurs at the same time as the rising edge of the second signal; and a filter means for averaging the flags generated by the flag generating means.
Claim 12
Dependent Claim
18 words
An apparatus as in claim 7 wherein the first delay interval is equal to the second delay interval.
Claim 13
Dependent Claim
84 words
An apparatus as in claim 7 for generating high current clock edges further comprising: third variable delay means having an input line to carry an input signal, an output line to carry an output signal and a control line to carry a control signal for delaying an input signal by the first delay interval to generate the output signal, the input line connected to the clock, the first delay interval responsive to the control signal, the output signal being the high current clock edge.
Claim 14
Independent Claim
96 words
A method for generating a clock edge referenced to a reference clock signal and an alternate clock signal, the apparatus comprising: delaying the reference clock signal in proportion to a control signal to generate a first signal and the clock edge; delaying the first signal in proportion to a control signal to generate a second signal; comparing the second signal to the alternate clock signal; and adjusting the control signal to increase the delay if the second signal leads the alternate clock signal or decrease the delay if the second signal lags the alternate clock signal.
Claim 15
Independent Claim
96 words
A method for generating a clock edge referenced to a reference clock signal and an alternate clock signal, the apparatus comprising: delaying the reference clock signal in proportion to a control signal to generate a first signal and the clock edge; delaying the first signal in proportion to a control signal to generate a second signal; comparing the second signal to the alternate clock signal; and adjusting the control signal to increase the delay if the second signal leads the alternate clock signal or decrease the delay if the second signal lags the alternate clock signal.
References Cited (Backward Citations)
US3553484A
Cited
US4090096A
Cited
US4463440A
Cited
US4489342A
Cited
US4504749A
Cited
US4496861A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-04-13 | 1990-10-13 | 1991-04-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-04-13 | 1994-10-13 | 1995-04-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-04-13 | 1998-10-13 | 1999-04-14 | $7700.00 | Window Closed / Lapsed |