Insulated gate field effect transistor

Claim 1

An insulated gate field effect transistor comprising: a semiconductor substrate of a first conduction type; a gate electrode formed over a predetermined channel region in the surface region overlying said semiconductor substrate; and a gate insulating film lying between said gate electrode and said semiconductor substrate; at least one of source and drain regions adjacent to said channel region comprising: a first impurity layer of a second conduction type and of a first predetermined depth, said first impurity layer having a first peak density and first impurity slope distribution of impurity values across said first predetermined depth of said first impurity layer, wherein said first impurity layer is formed with an impurity having a first impurity diffusion rate, and a second impurity layer of the second conduction type and of a second predetermined depth, said second impurity layer having a second peak density and a second impurity slope distribution of impurity values across said second predetermined depth of said second impurity layer, wherein said second impurity layer is formed with an impurity having a second impurity diffusion rate which is greater than the first impurity diffusion rate, wherein said second predetermined depth is greater than said first predetermined depth, wherein said first peak density is greater than said second peak density, and wherein said first impurity slope distribution is steeper than said second impurity slope distribution, and wherein said channel region has a first impurity distribution of the second conduction type lying in the vicinity of the surface of said semiconductor substrate and a second impurity distribution of the first conduction type and lying deeper in said substrate than said first impurity distribution, a concentration of said second impurity distribution being greater than an impurity concentration of said substrate.