Patent US4653030A successfully refreshed from Google Patents.
US4653030A
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Self refresh circuitry for dynamic memory
Assignee: Texas Instruments Inc
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Filing: 1984-08-31
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Granted: 1987-03-24
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Expires: 2004-08-31
Abstract
Abstract A semiconductor dynamic read/write memory of the multiplexed-address type employs an on-chip refresh counter which is activated by CAS-before-RAS sequence. This counter is made up of stages almost identical to the row address buffers so the same clocks can be used. Either the address input buffers or the refresh counter stages are gated into second-stage row address buffers, and carry feedback from these second stage buffers to the counter stages is used to increment the counter. The access time of the memory for normal read or write is not degraded by the refresh circuitry.
Inventors
- 👤 Tadashi Tachibana
- 👤 Chitranjan N. Reddy
- 👤 Ngai H. Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 21:03
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
176 words
A refresh address counter for a semiconductor dynamic memory device, said device having address enable inputs and having a plurality of address inputs Ao-An, comprising: a plurality of address input buffers, each receiving one of said address inputs in a first stage and producing high-level address signals (A, A) from a second stage, the output of each such first stage being coupled to the input of each second stage by first transfer means, a plurality of counter stages, one for each of said address input buffers, an output of each counter stage being coupled to said input of the second stage of the corresponding address input buffer by second transfer means, each said counter stage including incrementing input means, said incrementing means having an input coupled by third transfer means to said output of said second stage of the corresponding input buffer, control means responsive to said address enable inputs and operative to activate said first transfer means, or in the alternative to activate said second transfer means then later to activate said third transfer means.
Claim 2
Dependent Claim
176 words
A refresh address counter for a semiconductor dynamic memory device, said device having address enable inputs and having a plurality of address inputs Ao-An, comprising: a plurality of address input buffers, each receiving one of said address inputs in a first stage and producing high-level address signals (A, A) from a second stage, the output of each such first stage being coupled to the input of each second stage by first transfer means, a plurality of counter stages, one for each of said address input buffers, an output of each counter stage being coupled to said input of the second stage of the corresponding address input buffer by second transfer means, each said counter stage including incrementing input means, said incrementing means having an input coupled by third transfer means to said output of said second stage of the corresponding input buffer, control means responsive to said address enable inputs and operative to activate said first transfer means, or in the alternative to activate said second transfer means then later to activate said third transfer means.
Claim 3
Dependent Claim
20 words
A device according to claim 1 wherein said enable inputs are row address strobe RAS and column address strobe CAS.
Claim 4
Dependent Claim
36 words
A device according to claim 2 wherein said control means activates said first transfer means if RAS is activated before CAS, or alternatively activates said second then third transfer means if CAS is activated before RAS.
Claim 5
Dependent Claim
25 words
A device according to claim 1 wherein each or said address input buffers and counter stages are activated by a plurality of common clock voltages.
Claim 6
Dependent Claim
33 words
A device according to claim 4 wherein all of said address input buffers and all of said counter stages employ differential-input bistable circuits activated by said common clock voltages and having similar construction.
Claim 7
Dependent Claim
20 words
A device according to claim 5 wherein said enable inputs are row address strobe RAS and column address strobe CAS.
Claim 8
Dependent Claim
36 words
A device according to claim 6 wherein said control means activates said first transfer means if RAS is activated before CAS, or alternatively activates said second then third transfer means if CAS is activated before RAS.
Claim 9
Dependent Claim
144 words
An address counter for a semiconductor memory device having address control inputs, and having a plurality of address inputs, comprising: a plurality of address input buffer circuits, each buffer circuit receiving one of said address inputs in a first stage and producing high-level address output signals from a second stage, the output of each such first stage being coupled to the input of each second stage by first transfer means, a plurality of address counter stages, one for each of said address input buffer circuits, an output of each counter stage being coupled to said input of the second stage of the corresponding address input buffer circuit by second transfer means, each said counter stage including incrementing means, control means responsive to said address control inputs and operative to activate said first transfer means, or in the alternative to activate said second transfer means.
Claim 10
Dependent Claim
144 words
An address counter for a semiconductor memory device having address control inputs, and having a plurality of address inputs, comprising: a plurality of address input buffer circuits, each buffer circuit receiving one of said address inputs in a first stage and producing high-level address output signals from a second stage, the output of each such first stage being coupled to the input of each second stage by first transfer means, a plurality of address counter stages, one for each of said address input buffer circuits, an output of each counter stage being coupled to said input of the second stage of the corresponding address input buffer circuit by second transfer means, each said counter stage including incrementing means, control means responsive to said address control inputs and operative to activate said first transfer means, or in the alternative to activate said second transfer means.
Claim 11
Dependent Claim
21 words
A device according to claim 8 wherein said address control inputs are row address strobe RAS and column address strobe CAS.
Claim 12
Dependent Claim
34 words
A device according to claim 9 wherein said control means activates said first transfer means if RAS is activated before CAS, or alternatively activates said second transfer means if CAS is activated before RAS.
Claim 13
Dependent Claim
23 words
A device according to claim 8 wherein each of said address input buffer circuits and counter stages are activated by common clock voltages.
Claim 14
Dependent Claim
24 words
A device according to claim 11 wherein each of said address input buffer circuits and counter stages employ differential-input bistable circuits of similar construction.
Claim 15
Dependent Claim
21 words
A device according to claim 12 wherein said address control inputs are row address strobe RAS and column address strobe CAS.
Claim 16
Dependent Claim
34 words
A device according to claim 13 wherein said control means activates said first transfer means if RAS is activated before CAS, or alternatively activates said second transfer means if CAS is activated before RAS.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-23 | 1990-09-22 | 1991-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-23 | 1994-09-22 | 1995-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-23 | 1998-09-22 | 1999-03-24 | $7700.00 | Window Closed / Lapsed |