Multiple port memory with port decode error detector

Claim 2

For use in a multiple port memory system having addressable banks of storage modules, port selection through apparatus comprising: multiple port request receiving means for receiving requests for access to the memory system; priority means responsively coupled to said multiple port request receiving means for providing port code signals indicative of the request to be honored; a plurality of port means coupled to a corresponding plurality of requestors; multiplexor means commonly coupled to both said plurality of port means and said priority means, and said multiplexor means responsive to said port code signals and including means for generating decoded port code signals, each of said decoded port code signals providing information for selecting an associated one of said plurality of port means; and port code checking means coupled to said multiplexor means and responsive to said decoded port code signals for providing decode error signals when said decoded port code signals indicate the simultaneous selection of more than one of said plurality of port means.

Claim 3

Port selection through-checking apparatus as in claim 1 wherein said multiplexer means includes: port code register means coupled to said priority means for at least temporarily storing said port code signals; and decoder means coupled to said port code register means for providing a plurality of unique port enable signal combinations, one combination for each of said port code signals for selecting an associated one of said plurality of port means.

Claim 4

Port selection through-checking apparatus as in claim 2 wherein said port code checking means includes: port code enable comparison means coupled to said decoder means for providing an enabling signal when one and only one of said port enable signals are received, and for providing a disabling signal when more than one of said port enable signals are received; and output means coupled to said port code enable comparison means for providing decode error signals in response to said disabling signal.

Claim 5

Port selection through-checking apparatus as in claim 3 wherein said port code enable comparison means includes an Exclusive-OR circuit means having a plurality of input terminals coupled to said decoder means, with each of said plurality of input terminals coupled to receive an associated one of said unique port enable signals; and circuit means coupled to said Exclusive-OR circuit means for providing said enabling signal when any one of said port enable signals is different from all others of said port enable signals, and for providing said disabling signals when no single one of said port ensable signals is different from the others of said port enable signals.

Claim 6

Port selection through-checking apparatus as in claim 4 wherein said port code enable comparison means further includes: decode error latch means responsively coupled to said circuit means for at least temporarily storing said first and second signals, said decode error latch means having output terminal means for coupling to said output means.

Claim 7

Port selection through-checking apparatus as in claim 2 and further including: code error checking means responsively coupled to said priority means and to said multiplexer means for generating code error signals when said decoded port code signals do not exhibit a predetermined relationship to said port code signals.

Claim 8

Port selection through-checking apparatus as in claim 6 wherein said code error checking means includes: a plurality of first circuit means, each of said first circuit means responsively coupled to said decoder means for receiving predetermined ones of said port enable signals for providing port enable active signals indicative of the presence of any of said predetermined ones of said port enable signals; a plurality of port code comparison circuit means, each of said port code comparison circuit means coupled to an associated one of said plurality of first circuit means and responsively coupled to said priority means for receiving one of said port code signals for providing code error signals when said one of said port code signals has a predetermined mismatch relation to its associated one of said port enable active signals; and code error output means coupled to said plurality of port code comparison circuit means for transmitting said code error signals.

Claim 9

For use in a multiple access port memory system having addressable banks of storage modules and and plurality of requesters coupled to the multiple access ports for accessing the addressable banks of storage modules, a port selection through-checking apparatus comprising: a plurality of request receiving circuits coupled to said multiple access ports for receiving access request signals therethrough from said plurality of requestors; a plurality of priority circuits correspoondingly coupled to said plurality of request receiving circuits for prioritizing the received access request signals and for providing port code signals indicative of the port to be selected in response to the received port access requests; port code receiving means coupled to said plurality of priority circuits for receiving the port code signals therefrom; decode means coupled to said port code receiving means for decoding said port code signals and including means for providing to said plurality of access ports, one port enable signal indicative of the selected one of the plurality of access ports and also means for disabling all other non-selected access ports of said plurality of access ports; and port decode checking means coupled to said decode means for providing decode error signals when more than said one port enable signal is present.

Claim 10

For use in a multiple access port memory system having addressable banks of storage modules and and plurality of requesters coupled to the multiple access ports for accessing the addressable banks of storage modules, a port selection through-checking apparatus comprising: a plurality of request receiving circuits coupled to said multiple access ports for receiving access request signals therethrough from said plurality of requestors; a plurality of priority circuits correspoondingly coupled to said plurality of request receiving circuits for prioritizing the received access request signals and for providing port code signals indicative of the port to be selected in response to the received port access requests; port code receiving means coupled to said plurality of priority circuits for receiving the port code signals therefrom; decode means coupled to said port code receiving means for decoding said port code signals and including means for providing to said plurality of access ports, one port enable signal indicative of the selected one of the plurality of access ports and also means for disabling all other non-selected access ports of said plurality of access ports; and port decode checking means coupled to said decode means for providing decode error signals when more than said one port enable signal is present.

Claim 11

Port selection through-checking apparatus as in claim 8 wherein said port checking means includes: port code enable comparison means coupled to said decoder means for providing a first signal when one and only one of said port enable signals are present, and for providing a second signal when more than one said port enable signals are present; and output means coupled to said port code enable comparison means for providing decode error signals in response to said second signals.

Claim 12

Port selection through-checking apparatus as in claim 9 wherein said port code enable comparison means includes: Exclusive-OR circuit means having a plurality of input terminals coupled to said decoder means, with each of said plurality of input terminals connected to receive an associated one of said unique port enable signals.

Claim 13

Port selection through-checking apparatus as in claim 10 wherein said port code enable comparison means further includes: decode error latch means responsively coupled to said circuit means for at least temporarily storing said first and second signals, said decode error latch means having output terminal means for coupling to said output means.

Claim 14

Port selection through-checking apparatus as in claim 8 and further including: code error checking means responsively coupled to said priority means and to said multiplexer means for generating code error signals when said decoded port code signals do not exhibit a predetermined relationship to said port code signals.

Claim 15

Port selection through-checking apparatus as in claim 12 wherein said code error checking means includes: a plurality of first circuit means, each of said first circuit means responsively coupled to said decoder means for receiving predetermined ones of said port enable signals for providing port enable active signals indicative of the presence of any of said predetermined ones of said port enable signals; a plurality of port code comparison circuit means, each of said port code comparison circuit means coupled to an associated one of said plurality of first circuit means and responsively coupled to said port code receiving means for receiving one of said port code signals for providing code error signals when said one of said port code signals has a predetermined mismatch relation to said port enable active signals; and code error output means coupled to said plurality of port code comparison circuit means for transmitting said code error signals.

Claim 16

Port selection through-checking apparatus as in claim 8 wherein said decode means includes: port code register means for storing said port code signals, where said port code signals define a binary number; and decoder circuit means coupled to said port code register means and having 2 y output terminals, where `y` is a positive integer greater than zero, for decoding said port code signals to provide said one port enable signal on the selected one of said 2 y output terminals, and for disabling all others of said 2 y output terminals.