Support circuitry for multi-port systems

Claim 2

In a memory array having cells each of which is separately addressable from a plurality of write lines and is readable by a plurality of sets of low to high order bit lines, comprising: a memory cell array, a set of low to high order word decoders coupled to each cell of the array, a set of low to high order read heads coupled to each cell of the array, the lowest order read head being coupled to the cell via the lowest order bit lines and the higher read heads being respectively coupled to the cell, via respective higher order bit lines, said read heads being equal in number to the number of said word decoders, at least one inhibit and transfer circuit coupled to each of said higher order read heads, address comparison means coupled to said higher order word decoders and said higher order read heads, each of said inhibit and transfer circuit comprising a pair of bit activated transistors having their control electrodes respectively coupled to the low order bit lines, a pair of grounding transistors each being coupled between a respective high order bit line and ground, and switching transistors coupled in parallel with the bit line activated transistors and respectively coupled to the control electrode of the grounding transistors to selectively control one of the grounding transistors and transfer the state of a lower order bit line to a higher order bit line.

Claim 3

In a memory array having cells each of which is separately addressable from a plurality of write lines and is readable by a plurality of sets of low to high order bit lines, comprising: a memory cell array, a set of low to high order word decoders coupled to each cell of the array, a set of low to high order read heads coupled to each cell of the array, via said plurality of bit lines, said higher order read heads being equal in number to the number of higher order word decoders, at least one inhibit and transfer circuit coupled to each of said higher order read heads, the number of said inhibit and transfer circuits coupled to the higher order read heads being one less than the order of the bit lines to which the read head is coupled, address comparison means coupled to said higher order word decoders and said higher order read heads, each of said inhibit and transfer circuit comprising a pair of bit activated transistors having their control electrodes respectively coupled to the low order bit lines, a pair of grounding transistors each being coupled between a respective high order bit line and ground, and a switching transistor coupled in parallel with the bit line activated transistors and to the control electrode of the grounding transistors to selectively control one of the grounding transistors and transfer the state of a lower order bit line to a higher order bit line.

Claim 4

In a memory array having cells each of which is separately addressable from a plurality of write lines and is readable by a plurality of sets of low to high order bit lines, comprising: a memory cell array, a set of low to high order word decoders coupled to each cell of the array, a set of low to high order read heads coupled to each cell of the array, via said plurality of bit lines, said higher order read heads being equal in number to the number of higher order word decoders, at least one inhibit and transfer circuit coupled to each of said higher order read heads, the number of said inhibit and transfer circuits coupled to the higher order read heads being one less than the order of the bit lines to which the read head is coupled, address comparison means coupled to said higher order word decoders and said higher order read heads, each of said inhibit and transfer circuit comprising a pair of bit activated transistors having their control electrodes respectively coupled to the low order bit lines, a pair of grounding transistors each being coupled between a respective high order bit line and ground, and a switching transistor coupled in parallel with the bit line activated transistors and to the control electrode of the grounding transistors to selectively control one of the grounding transistors and transfer the state of a lower order bit line to a higher order bit line.

Claim 5

The array of claim 1 wherein each of said inhibit and transfer circuits are coupled to a clocked buffer circuit driven by said comparison means.

Claim 6

The memory array of claim 1 wherein said address comparison means, in the event of a compare between said addresses, provides a signal to said higher order word decoders to disable selected ones of said higher order word decoders, and to said clocked buffer circuits to switch said inhibit and transfer circuits to inhibit selected ones of said higher order read heads from reading the higher order bit lines of the set of simultaneously addressed bit lines from the cell while simultaneously transferring the information of the lowest order of said set of simultaneously addressed bit lines to the highest order of simultaneously addressed bit lines.

Claim 7

In a memory array which is separately addressable from a plurality of write lines and readable by a plurality of bit lines comprising: a memory cell array, each cell being coupled to sets of low to high order bit lines, a plurality of sets of low to high order decoders, coupled to the cells of the array, a plurality of sets of low to high order read heads equal in number to the number of word decoders coupled to the cells of the array, and having a plurality of output read lines equal to the number of said word decoders, each of said high order read heads being connected to its respective set of bit lines and coupled to all sets of lower order bit lines, at least one inhibit and transfer circuit coupled to each of the higher order read heads, a plurality of comparator means for comparing the address inputs to the word decoders, said comparator means being coupled to the word decoders and the inhibit and transfer circuits and in the event of a compare disabling selected ones of word decoders, and activating selected ones of the inhibit and transfer circuits, said inhibit and transfer circuits setting the higher order of bit lines to the same state as the lowest order bit line set having the same address as the higher order bit lines to which the read head is connected.

Claim 8

In a memory array which is separately addressable from a plurality of write lines and readable by a plurality of bit lines comprising: a memory cell array, each cell being coupled to sets of low to high order bit lines, a plurality of sets of low to high order decoders, coupled to the cells of the array, a plurality of sets of low to high order read heads equal in number to the number of word decoders coupled to the cells of the array, and having a plurality of output read lines equal to the number of said word decoders, each of said high order read heads being connected to its respective set of bit lines and coupled to all sets of lower order bit lines, at least one inhibit and transfer circuit coupled to each of the higher order read heads, a plurality of comparator means for comparing the address inputs to the word decoders, said comparator means being coupled to the word decoders and the inhibit and transfer circuits and in the event of a compare disabling selected ones of word decoders, and activating selected ones of the inhibit and transfer circuits, said inhibit and transfer circuits setting the higher order of bit lines to the same state as the lowest order bit line set having the same address as the higher order bit lines to which the read head is connected.

Claim 9

An inhibit and transfer circuit comprising: a pair of bit activated transistors having their control electrodes coupled to a first source of bit signals, a pair of grounding transistors each being coupled between a second source of bit signals and ground, and switching transistors coupled in parallel with the bit activated transistors and respectively coupled to the control electrodes of the grounding transistors, to selectively control one of the grounding transistors to selectively force the said second source of bit signals to be identical to the first source of signals.

Claim 10

An inhibit and transfer circuit comprising: a pair of bit activated transistors having their control electrodes coupled to a first source of bit signals, a pair of grounding transistors each being coupled between a second source of bit signals and ground, and switching transistors coupled in parallel with the bit activated transistors and respectively coupled to the control electrodes of the grounding transistors, to selectively control one of the grounding transistors to selectively force the said second source of bit signals to be identical to the first source of signals.