Patent US5072213A successfully refreshed from Google Patents.
Patent US4648909A successfully refreshed from Google Patents.
US4648909A
Expired / Lapsed
US
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Fabrication process employing special masks for the manufacture of high speed bipolar analog integrated circuits
Assignee: Fairchild Semiconductor Corp
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Filing: 1984-11-28
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Granted: 1987-03-10
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Expires: 2004-11-28
Abstract
Abstract A fabrication process for integrated circuits having linear bipolar transistors and other circuit elements. The process defines collector contact 32, base 34, and isolation 36 regions in one masking operation. Subsequent masking layers of photoresist 40, 42, 46 are used to shield selected regions during implantation of exposed regions. Circuit density is improved through the use of aluminum doped isolation regions 36. The base region is doped in a single ion implantation step, which is followed by low temperature deposition of a covering oxide layer 48.
Inventors
- 👤 Surinder Krishna
- 👤 Kulwant Egan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:34
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30; Y; Y10; Y10S; Y10S148/00; Y10S148/01
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
267 words
A method of fabricating a bipolar transistor in a wafer having a silicon substrate of first conductivity type, an epitaxial layer of second conductivity type and a buried layer of second conductivity type disposed between a portion of the substrate and the epitaxial layer, the method comprising: forming a first mask over the epitaxial layer having openings therein to define a collector contact, a base, and an isolation region; in a desired sequence performing the steps of: covering at least one, but not all, of the openings for the collector contact, the base, and the isolation region with a protective layer, introducing desired conductivity type impurity into the epitaxial layer through whichever opening is not covered with the protective layer, repeating the above steps of covering and introducing until desired conductivity type impurity has been introduced into the epitaxial layer through all of the openings, the desired conductivity type being first conductivity type for the isolation and base regions and second conductivity type for the collector contact region; forming a second mask over the epitaxial layer having an opening therein to define an emitter region situated within the base region and openings therein for ohmic connections to each of the base region, the collector contact and the isolation region; covering at least the openings for ohmic connections to the base region and isolation region; introducing second conductivity type impurity into the epitaxial layer through at least the emitter opening; and forming electrical connections to all of the emitter region, the base region, the collector contact region and the isolation region through the openings in the second mask.
Claim 2
Independent Claim
267 words
A method of fabricating a bipolar transistor in a wafer having a silicon substrate of first conductivity type, an epitaxial layer of second conductivity type and a buried layer of second conductivity type disposed between a portion of the substrate and the epitaxial layer, the method comprising: forming a first mask over the epitaxial layer having openings therein to define a collector contact, a base, and an isolation region; in a desired sequence performing the steps of: covering at least one, but not all, of the openings for the collector contact, the base, and the isolation region with a protective layer, introducing desired conductivity type impurity into the epitaxial layer through whichever opening is not covered with the protective layer, repeating the above steps of covering and introducing until desired conductivity type impurity has been introduced into the epitaxial layer through all of the openings, the desired conductivity type being first conductivity type for the isolation and base regions and second conductivity type for the collector contact region; forming a second mask over the epitaxial layer having an opening therein to define an emitter region situated within the base region and openings therein for ohmic connections to each of the base region, the collector contact and the isolation region; covering at least the openings for ohmic connections to the base region and isolation region; introducing second conductivity type impurity into the epitaxial layer through at least the emitter opening; and forming electrical connections to all of the emitter region, the base region, the collector contact region and the isolation region through the openings in the second mask.
Claim 3
Dependent Claim
36 words
A method as in claim 1, wherein the step of forming a first mask comprises: forming a layer of silicon dioxide over the epitaxial layer; and depositing a layer of silicon nitride over the silicon dioxide.
Claim 4
Dependent Claim
115 words
A method as in claim 1 wherein the step of repeating the above steps of covering and introducing until desired conductivity type impurity has been introduced comprises: covering the base and isolation region openings, and introducing second conductivity type impurity into the epitaxial layer through the collector contact opening; covering the collector contact opening and the base opening but not the isolation region opening, and introducing first conductivity type impurity into the epitaxial layer through the isolation region opening; and covering the collector contact opening but not the base opening and not the isolation region opening, and introducing first conductivity type impurity into the epitaxial layer through the base opening and the isolation region opening.
Claim 5
Dependent Claim
35 words
A method as in claim 1 wherein the step of covering at least the openings for ohmic connections comprises covering only the openings for ohmic connections, and not covering the opening for the collector contact.
Claim 6
Dependent Claim
37 words
A method as in claim 1 wherein the step of forming electrical connections comprises depositing a layer of electrically conductive material over the second mask and onto the epitaxial layer through the openings in the second mask.
Claim 7
Dependent Claim
47 words
A method as in claim 1 wherein the opening in the second mask to define the ohmic connection to the base extends outside the base, and wherein the electrical connection to the base contacts both the base and the epitaxial layer to thereby form a Schottky diode.
Claim 8
Dependent Claim
19 words
A method as in claim 1 wherein the first mask further includes an opening to define a capacitor region.
Claim 9
Dependent Claim
27 words
A method as in claim 2 wherein the step of forming a first mask further comprises etching openings through the layers of silicon dioxide and silicon nitride.
Claim 10
Dependent Claim
37 words
A method as in claim 3 wherein the step of introducing first conductivity type impurity into the epitaxial layer through the isolation region opening further comprises introducing aluminum into the epitaxial layer through the isolation region opening.
Claim 11
Dependent Claim
36 words
A method as in claim 3 wherein prior to the step of covering the base and the isolation region openings a layer of silicon dioxide is formed on the epitaxial layer in all of the openings.
Claim 12
Dependent Claim
46 words
A method as in claim 4 wherein the step of introducing second conductivity type impurity into the epitaxial layer through at least the emitter opening further comprises introducing second conductivity type impurity into the epitaxial layer through both the emitter opening and the collector contact opening.
Claim 13
Dependent Claim
32 words
A method as in claim 7 wherein when impurity is introduced into the epitaxial layer through the collector contact opening, impurity is also introduced into the epitaxial layer through the capacitor opening.
Claim 14
Dependent Claim
46 words
A method as in claim 9 wherein the step of introducing first conductivity type impurity into the epitaxial layer through the base opening and the isolation region opening further comprises introducing boron into the epitaxial layer through both the isolation opening and the base region opening.
Claim 15
Independent Claim
254 words
A method of fabricating a bipolar transistor in a wafer having a silicon substrate of first conductivity type, an epitaxial layer of second conductivity type and a buried layer of second conductivity type disposed between a portion of the substrate and the epitaxial layer, the method comprising: forming a first mask over the epitaxial layer having openings therein to define a collector contact, a base, and an isolation region; covering the base and isolation region openings, then introducing second conductivity type impurity into the epitaxial layer through thhe collector contact opening; covering the collector contact opening and the base opening, but not the isolation region opening, then introducing first conductivity type impurity into the epitaxial layer through the isolation region opening; covering the collector contact opening, but not the isolation region opening and not the base region opening, then introducing first conductivity type impurity into the epitaxial layer through both the base region opening and the isolation region opening; forming a second mask over the epitaxial layer having an opening therein to define an emitter region within the base region and openings therein for ohmic connections to each of the base region, the collector contact and the isolation region; covering at least the openings for ohmic connections to the base region and isolation region; introducing second conductivity type impurity into the epitaxial layer through at least the emitter opening; and forming electrical connections to all of the emitter region, base region, collector contact region and isolation region through the openings in the second mask.
Claim 16
Independent Claim
254 words
A method of fabricating a bipolar transistor in a wafer having a silicon substrate of first conductivity type, an epitaxial layer of second conductivity type and a buried layer of second conductivity type disposed between a portion of the substrate and the epitaxial layer, the method comprising: forming a first mask over the epitaxial layer having openings therein to define a collector contact, a base, and an isolation region; covering the base and isolation region openings, then introducing second conductivity type impurity into the epitaxial layer through thhe collector contact opening; covering the collector contact opening and the base opening, but not the isolation region opening, then introducing first conductivity type impurity into the epitaxial layer through the isolation region opening; covering the collector contact opening, but not the isolation region opening and not the base region opening, then introducing first conductivity type impurity into the epitaxial layer through both the base region opening and the isolation region opening; forming a second mask over the epitaxial layer having an opening therein to define an emitter region within the base region and openings therein for ohmic connections to each of the base region, the collector contact and the isolation region; covering at least the openings for ohmic connections to the base region and isolation region; introducing second conductivity type impurity into the epitaxial layer through at least the emitter opening; and forming electrical connections to all of the emitter region, base region, collector contact region and isolation region through the openings in the second mask.
Claim 17
Dependent Claim
45 words
A method as in claim 14 wherein following the step of forming a first mask and prior to the step of covering the base and isolation region, a step is performed comprising forming a layer of insulating material over the epitaxial layer in the openings.
Claim 18
Dependent Claim
27 words
A method as in claim 14 wherein the step of introducing second conductivity type impurity into the epitaxial layer through the collector contact opening comprises implanting phosphorus.
Claim 19
Dependent Claim
27 words
A method as in claim 14 wherein the step of introducing first conductivity type impurity into the epitaxial layer through the isolation region opening comprises implanting aluminum.
Claim 20
Dependent Claim
42 words
A method as in claim 14 wherein the step of introducing second conductivity type impurity into the epitaxial layer through at least the emitter opening comprises implanting phosphorus into the epitaxial layer through both the emitter opening and the collector contact opening.
Claim 21
Dependent Claim
53 words
A method as in claim 14 wherein the step of forming a first mask further comprises defining a capacitor region, and the step of introducing second conductivity type impurity into the epitaxial layer through the collector contact opening further comprises introducing second conductivity type impurity into the epitaxial layer through the capacitor opening.
Claim 22
Dependent Claim
33 words
A method as in claim 14 wherein the epitaxial layer has a thickness of between 2.2 and 2.7 microns, a resistivity of between 0.6 and 1.0 ohm centimeters, and is doped with phosphorus.
Claim 23
Dependent Claim
38 words
A method as in claim 14 wherein the step of forming a first mask comprises: forming a layer of silicon dioxide on the epitaxial layer; and forming a layer of silicon nitride on the layer of silicon dioxide.
Claim 24
Dependent Claim
13 words
A method as in claim 15 wherein the insulating material comprises silicon dioxide.
Claim 25
Dependent Claim
31 words
A method as in claim 17 wherein the step of introducing first conductivity type impurity into the epitaxial layer through the base opening and the isolation region opening comprises implanting boron.
Claim 26
Dependent Claim
27 words
A method as in claim 21 wherein the step of forming a second mask comprises forming at least one layer of silicon dioxide on the epitaxial layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-09 | 1990-09-08 | 1991-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-09 | 1994-09-08 | 1995-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-09 | 1998-09-08 | 1999-03-10 | $7700.00 | Window Closed / Lapsed |