Decoder circuit for a static random access memory

Claim 1

A decoder circuit for an integrated monolithic static random access memory, which circuit comprises a first logic NOR-gate (P1) formed by a first row of field effect transistors whose gate electrodes receive "n" coded memory address signals; the sources of said first row of transistors being connected to ground and the drains thereof being connected in common to an output terminal of the first NOR-gate (P1), such output terminal being connected by a load to a source of supply voltage V DD1 and being further connected to the gate electrode of a transistor of an output inverter stage; the source of the inverter stage transistor constituting the output terminal of the decoder circuit and being connected to the common drains of a second row of transistors which form a second NOR-gate (P2); the drain of the inverter stage transistor being connected to a source of supply voltage V DD2 ; the sources of the transistors of the second row being connected to ground and the gate electrodes thereof receiving the "n" coded address signals; each of said first and second rows of transistors comprising a selection transistor being parallel-connected to the respective rows of transistors and having a gate electrode for receiving a common chip-enable selection signal (SB), whereby said chip-enable selection signal (SB) being applied to the selection transistors after the coded memory address signals are applied to each of the two NOR-gates (P1, P2), thereby achieving reduced access time for the random access memory.