Method of making precision high-value MOS capacitors

Claim 2

An improved method for forming a capacitor on an integrated circuit structure comprising: forming a first polycrystalline silicon layer; implanting n-conductivity type ions into the first polycrystalline silicon layer at an implant energy between approximately 80 and 100 keV; oxidizing the surface, of the polycrystalline silicon layer to form a uniform interpoly oxide layer, the oxidation being at a temperature which, for the implant dosage of the n-conductivity type ions, will make the interpoly oxide layer between approximately 770 and 2000 Angstroms thick; annealing the interpoly oxide layer in a gaseous mixture including HCl at a temperature of approximately 1100° C.; and forming a second polycrystalline silicon layer over said interpoly oxide layer.

Claim 3

The method of claim 1 wherein the first polycrystalline silicon layer is formed over an insulating layer.

Claim 4

The method of claim 1 wherein the n-conductivity ions comprise one of phosphorus or arsenic.

Claim 5

The method of claim 1 wherein the first polycrystalline silicon layer is formed at a temperature of approximately 600° C.

Claim 6

The method of claim 1 wherein the n-conductivity type ions comprise arsenic.

Claim 7

The method of claim 1 wherein the n-conductivity type ions comprise phosphorous.

Claim 8

The method of claim 2 wherein the insulating layer comprises a field isolation region of silicon dioxide approximately 1400 Angstroms thick.

Claim 9

An improved method for forming a capacitor on a silicon dioxide insulating layer on an integrated circuit structure, the method comprising: forming a first polycrystalline silicon layer at a temperature of approximately 600° C.; implanting n-conductivity type ions into the first polycrystalline silicon layer at an implant dosage of approximately 3×10 15 ions/cm 2 and an implant energy between approximately 80 and 100 keV; oxidizing the surface of the first polycrystalline silicon layer to form an interpoly oxide layer, the oxidizing step comprising: inserting the integrated circuit structure into a diffusion furnace containing N 2 and O 2 at standard pressure and a flow rate of approximately 300 cubic centimeters per minute at approximately 850° C.; increasing the temperature inside the diffusion furnace from approximately 850° C. to approximately 1000° C. at a rate of approximately 8° C. per minute; replacing the N 2 and O 2 with O 2 at standard pressure and a flow rate of approximately 3000 cubic centimeters per minute for approximately 20 minutes; replacing the O 2 with a mixture of approximately 3% HCl and 97% O 2 for approximately 21 minutes; replacing the O 2 and HCl with N 2 at standard pressure and a flow rate of approximately 5000 cubic centimeters per minute; increasing the temperature inside the diffusion furnace to approximately 1100° C. over approximately a 20 minute period; replacing the N 2 with a mixture of approximately 95.4% N 2 , 3.4% O 2 and 1.2% HCl for approximately 60 minutes; replacing the mixture with N 2 at standard pressure and a flow rate of approximately 5000 cubic centimeters per minute; decreasing the temperature inside the diffusion furnace to approximately 850° C. over a period of approximately 60 minutes; and forming a second polycrystalline silicon layer over the interpoly oxide layer.

Claim 10

An improved method for forming a capacitor on a silicon dioxide insulating layer on an integrated circuit structure, the method comprising: forming a first polycrystalline silicon layer at a temperature of approximately 600° C.; implanting n-conductivity type ions into the first polycrystalline silicon layer at an implant dosage of approximately 3×10 15 ions/cm 2 and an implant energy between approximately 80 and 100 keV; oxidizing the surface of the first polycrystalline silicon layer to form an interpoly oxide layer, the oxidizing step comprising: inserting the integrated circuit structure into a diffusion furnace containing N 2 and O 2 at standard pressure and a flow rate of approximately 300 cubic centimeters per minute at approximately 850° C.; increasing the temperature inside the diffusion furnace from approximately 850° C. to approximately 1000° C. at a rate of approximately 8° C. per minute; replacing the N 2 and O 2 with O 2 at standard pressure and a flow rate of approximately 3000 cubic centimeters per minute for approximately 20 minutes; replacing the O 2 with a mixture of approximately 3% HCl and 97% O 2 for approximately 21 minutes; replacing the O 2 and HCl with N 2 at standard pressure and a flow rate of approximately 5000 cubic centimeters per minute; increasing the temperature inside the diffusion furnace to approximately 1100° C. over approximately a 20 minute period; replacing the N 2 with a mixture of approximately 95.4% N 2 , 3.4% O 2 and 1.2% HCl for approximately 60 minutes; replacing the mixture with N 2 at standard pressure and a flow rate of approximately 5000 cubic centimeters per minute; decreasing the temperature inside the diffusion furnace to approximately 850° C. over a period of approximately 60 minutes; and forming a second polycrystalline silicon layer over the interpoly oxide layer.

Claim 11

An improved method for forming a capacitor on an integrated circuit structure comprising: forming a first polycrystalline silicon layer; implanting n-conductivity type ions into the first polycrystalline silicon layer at an implant energy between approximately 80 and 100 keV; inserting the integrated circuit structure into a diffusion furnace containing N 2 and O 2 at standard pressure and a flow rate of approximately 300 cubic centimeters per minute at approximately 850° C.; increasing the temperature inside the diffusion furnace from approximately 850° C. to approximately 1000° C. at a rate of approximately 8° C. per minute; replacing the N 2 and O 2 with O 2 at standard pressure and a flow of approximately 3000 cubic centimeters per minute for approximately 20 minutes; replacing the O 2 with a mixture of approximately 3% HCl and 97% O 2 for approximately 21 minutes; replacing the O 2 and HCl with N 2 at standard pressure and a flow rate of approximately 5000 cubic centimeters per minute; increasing the temperature inside the diffusion furnace to approximately 1100° C. over approximately a 20 minute period; replacing the N 2 with a mixture of approximately 95.4% N 2 , 3.4% O 2 and 1.2% HCl for approximately 60 minutes; replacing the mixture with N 2 at standard pressure and a flow rate of approximately 5000 cubic centimeters per minute; decreasing the temperature inside the diffusion furnace to approximately 850° C. over a period of approximately 60 minutes; removing the integrated circuit structure from the diffusion furnace; and forming a second polycrystalline silicon layer over said interpoly oxide layer.

Claim 12

An improved method for forming a capacitor on an integrated circuit structure comprising: forming a first polycrystalline silicon layer; implanting n-conductivity type ions into the first polycrystalline silicon layer at an implant energy between approximately 80 and 100 keV; inserting the integrated circuit structure into a diffusion furnace containing N 2 and O 2 at standard pressure and a flow rate of approximately 300 cubic centimeters per minute at approximately 850° C.; increasing the temperature inside the diffusion furnace from approximately 850° C. to approximately 1000° C. at a rate of approximately 8° C. per minute; replacing the N 2 and O 2 with O 2 at standard pressure and a flow of approximately 3000 cubic centimeters per minute for approximately 20 minutes; replacing the O 2 with a mixture of approximately 3% HCl and 97% O 2 for approximately 21 minutes; replacing the O 2 and HCl with N 2 at standard pressure and a flow rate of approximately 5000 cubic centimeters per minute; increasing the temperature inside the diffusion furnace to approximately 1100° C. over approximately a 20 minute period; replacing the N 2 with a mixture of approximately 95.4% N 2 , 3.4% O 2 and 1.2% HCl for approximately 60 minutes; replacing the mixture with N 2 at standard pressure and a flow rate of approximately 5000 cubic centimeters per minute; decreasing the temperature inside the diffusion furnace to approximately 850° C. over a period of approximately 60 minutes; removing the integrated circuit structure from the diffusion furnace; and forming a second polycrystalline silicon layer over said interpoly oxide layer.