Process for fabricating semiconductor integrated circuit device

Claim 1

A process for fabricating a semiconductor integrated circuit device, comprising the steps of: (a) providing a semiconductor substrate, said substrate having a well region in a surface region of the substrate, leaving a portion of the semiconductor substrate surface region in which the well region is not formed, the well region being of conductivity type opposite that of said portion of the semiconductor substrate surface region, said substrate having gate oxide films, formed on said well region and on said portion, where semiconductor elements are to be formed; (b) forming gate electrodes for metal insulator semiconductor field effect transistors both on the gate oxide films on the well region and on said portion of the semiconductor substrate surface region, each gate electrode having opposed sides and adapted to have a channel region in a surface region of the respective well region and semiconductor substrate beneath each gate electrode; (c) forming side wall spacers at each side of each of the gate electrodes; (d) introducing a first impurity, of conductivity type the same as that of the semiconductor substrate, into the well region without introduction into said portion of the semiconductor substrate surface region, using the gate electrode on the well region and its respective side wall spacers as a mask; (e) introducing a second impurity, of conductivity type the same as that of said first impurity, into the well region without introduction into said portion of the semiconductor substrate surface region, using the gate electrode on the well region and its respective side wall spacers as a mask, the second impurity having a lower diffusion speed in the well region than the first impurity; (f) diffusing the first and second impurities into the well region, to form first and second semiconductor regions, respectively. therein, whereby, due to the different diffusion speeds in the well region, the first semiconductor region covers the second semiconductor region; and (g) introducing a third impurity, of conductivity type the same as the well region, into said portion of the semiconductor substrate surface region, using the gate electrode on said portion and its respective side wall spacers as masks, so as to form third semiconductor regions, whereby complementary metal insulator semiconductor field effect transistor can be formed in the semiconductor substrate, and whereby the side wall spacers suppress the first, second and third semiconductor regions from extending underneath the gate electrodes.