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Patent US4633183A successfully refreshed from Google Patents.
US4633183A
Expired / Lapsed
US
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Constant resolution frequency synthesizer
Assignee: Hayes Microcomputer Products Inc
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Filing: 1985-02-28
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Granted: 1986-12-30
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Expires: 2005-02-28
Abstract
Abstract A frequency synthesizer which has a constant resolution over an octave frequency range is disclosed. The frequency synthesizer has a presettable high speed counter, a low speed counter, an adjusting counter, and a count selector. The low speed counter provides a first output signal whose frequency is rapidly alternated between two closely-spaced frequencies so that the average frequency of the output signal is the desired frequency. The adjusting counter determines the period of time that each of the closely-spaced frequencies is present at the output. The count selector determines the frequency of each of the two closely-spaced frequencies. The frequency synthesizer also has a phase splitter and provides a second output signal which is also of the desired frequency but which is phase-shifted by ninety degrees from the first output signal.
Inventors
- 👤 Dale A. Heatherington
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:03
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/197
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
159 words
A frequency synthesizer for generating an output signal at a predetermined frequency comprising: a counter including a first predetermined number of high speed stages having count control inputs, and a second predetermined number of low speed stages; output means connected to at least one of said low speed stages for providing said output signal; input means for accepting an externally provided frequency control code; and adjusting means responsive to said output signal and said frequency control code for providing correction information to a count selector during each occurrence of a predetermined number of cycles of said output signal; said count selector being responsive to said frequency correction information to provide a first count control signal to said count control inputs for a first fraction of said predetermined number of cycles of said output signal, and a second count control signal to said count control inputs for a second fraction of said predetermined number of cycles of said output signal.
Claim 2
Dependent Claim
159 words
A frequency synthesizer for generating an output signal at a predetermined frequency comprising: a counter including a first predetermined number of high speed stages having count control inputs, and a second predetermined number of low speed stages; output means connected to at least one of said low speed stages for providing said output signal; input means for accepting an externally provided frequency control code; and adjusting means responsive to said output signal and said frequency control code for providing correction information to a count selector during each occurrence of a predetermined number of cycles of said output signal; said count selector being responsive to said frequency correction information to provide a first count control signal to said count control inputs for a first fraction of said predetermined number of cycles of said output signal, and a second count control signal to said count control inputs for a second fraction of said predetermined number of cycles of said output signal.
Claim 3
Dependent Claim
16 words
A frequency synthesizer as recited in claim 1 wherein: said adjusting means includes an adjusting counter.
Claim 4
Dependent Claim
87 words
A frequency synthesizer as recited in claim 2 wherein: said adjusting counter is an M stage counter, M being an integer greater than one; said low speed stages include K stages between the output of the most significant stage of said high speed stages and said output means, K being an integer greater than 0; said adjusting counter is clocked from said most significant stage of said high speed stages; and said predetermined number of cycles of said output is equal to 2 M /2 K .
Claim 5
Dependent Claim
39 words
A frequency synthesizer as recited in claim 2 further comprising: loading means for loading said adjusting counter with binary data corresponding to said frequency control code upon each occurrence of said predetermined number of cycles of said output signal.
Claim 6
Dependent Claim
61 words
A frequency synthesizer as recited in claim 2 wherein: said count selector comprises means for detecting a first count condition of said adjusting counter to provide said first count control signal during said first count condition, and means for detecting a second distinct count condition of said adjusting counter and providing said second count control signal during said second count condition.
Claim 7
Dependent Claim
146 words
A frequency synthesizer for generating an output signal at a predetermined frequency comprising: a counter including a first predetermined number of high speed stages having count control inputs, and a second predetermined number of low speed stages; output means connected to at least one of said low speed stages for providing said output signal; input means connected to at least one of said low speed stages for periodically latching an externally provided frequency control code to provide a latched frequency control code; and adjusting and count selector means connected to said input means and responsive to said latched frequency control code to cause said high speed stages to count through a first number of count cycles at a first division ratio, and subsequently to count through a second number of count cycles at a second division ratio, in response to each said latched frequency control code.
Claim 8
Dependent Claim
146 words
A frequency synthesizer for generating an output signal at a predetermined frequency comprising: a counter including a first predetermined number of high speed stages having count control inputs, and a second predetermined number of low speed stages; output means connected to at least one of said low speed stages for providing said output signal; input means connected to at least one of said low speed stages for periodically latching an externally provided frequency control code to provide a latched frequency control code; and adjusting and count selector means connected to said input means and responsive to said latched frequency control code to cause said high speed stages to count through a first number of count cycles at a first division ratio, and subsequently to count through a second number of count cycles at a second division ratio, in response to each said latched frequency control code.
Claim 9
Dependent Claim
143 words
A frequency synthesizer for generating an output signal at a predetermined frequency comprising: a counter including a first predetermined number of high speed stages having count control inputs, and a second predetermined number of low speed stages; means connected to at least one of said low speed stages for providing said output signal; adjusting means responsive to said output signal for providing frequency correction information to a count selector upon each occurrence of a predetermined number of cycles of said output signal; said count selector being responsive to said frequency correction information to provide a first count control signal to said count control inputs for a first fraction of said predetermined number of cycles of said output signal, and a second count control signal to said count control inputs for a second fraction of said predetermined number of cycles of said output signal.
Claim 10
Dependent Claim
143 words
A frequency synthesizer for generating an output signal at a predetermined frequency comprising: a counter including a first predetermined number of high speed stages having count control inputs, and a second predetermined number of low speed stages; means connected to at least one of said low speed stages for providing said output signal; adjusting means responsive to said output signal for providing frequency correction information to a count selector upon each occurrence of a predetermined number of cycles of said output signal; said count selector being responsive to said frequency correction information to provide a first count control signal to said count control inputs for a first fraction of said predetermined number of cycles of said output signal, and a second count control signal to said count control inputs for a second fraction of said predetermined number of cycles of said output signal.
Claim 11
Dependent Claim
15 words
A frequency synthesizer as recited in claim 7 wherein: said adjusting means includes a counter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-29 | 1990-06-30 | 1990-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-29 | 1994-06-30 | 1994-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-29 | 1998-06-30 | 1998-12-30 | $7700.00 | Window Closed / Lapsed |