US4110567A
Expired / Lapsed
US
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Multi-frequency generator using digital technique
Assignee: International Standard Electric Corp
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Filing: 1977-03-14
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Granted: 1978-08-29
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Expires: 1997-03-14
Abstract
Abstract A circuit for producing sinusoidal wave-forms representative of signals used in voiceband signaling for telephone dialing, frequently referred to as DTMF signaling. A sine wave is broken into a predetermined number of time increments. The amplitude changes for each increment may be indicated in the form of a binary digital word for a quadrant of the curve. The remaining quadrants will exhibit essentially the same change characteristics at like time increments with only the bit order reversed or the polarity changed thus, the basic binary word is unchanged for each quadrant. A programmable memory is set to produce the binary word at a selected clock rate. In this way, synthesis of a plurality of sine waves may be readily produced using delta modulation techniques. For all sine curves, the number of time increments remains the same, the rate of pulsing the increments is varied responsive to the keyboard signals generated. For telephone use, a high and a low signal are synthesized at essentially the same time. These signals may further be combined on a single output for transmission to the tone receiver.
Inventors
- 👤 Donald J. Boucher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:20
CPC Classifications
H; H04; H04M; H04M1/00; H04M1/26; H04M1/30; H04M1/50; H04M1/505
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
186 words
A telephone signaling circuit for generating an output tone frequency in response to selection of one of a plurality of signal controllers with each controller representing at least one tone frequency, said circuit including a base frequency generator, a variable modulo counter circuit for dividing the base frequency generated by a selected modulus responsive to the controller selected for emitting pulse signals, a further counter serially disposed to receive said pulse signals, said further counter operative to divide the frequency of received pulses by a predetermined number for emitting a stream of pulses at a rate determined by said base frequency and said predetermined number, a programmable logic array for coding said pulses at said rate into a programmed digital binary word, said word being comprised of binary digital bits of either of two types to approximate the changes in the sine curve of a tone signal being generated, said array normally biased to transmit one type of bit responsive to each successive pulse of said stream and transmitting the other type at predetermined locations in said word, responsive to a stored pattern within said array.
Claim 2
Dependent Claim
186 words
A telephone signaling circuit for generating an output tone frequency in response to selection of one of a plurality of signal controllers with each controller representing at least one tone frequency, said circuit including a base frequency generator, a variable modulo counter circuit for dividing the base frequency generated by a selected modulus responsive to the controller selected for emitting pulse signals, a further counter serially disposed to receive said pulse signals, said further counter operative to divide the frequency of received pulses by a predetermined number for emitting a stream of pulses at a rate determined by said base frequency and said predetermined number, a programmable logic array for coding said pulses at said rate into a programmed digital binary word, said word being comprised of binary digital bits of either of two types to approximate the changes in the sine curve of a tone signal being generated, said array normally biased to transmit one type of bit responsive to each successive pulse of said stream and transmitting the other type at predetermined locations in said word, responsive to a stored pattern within said array.
Claim 3
Dependent Claim
37 words
A signaling circuit as claimed in claim 1, in which the curve of said tone signal comprises a sine wave having four quadrants, with said further counter being bidirectional to cycle for each quadrant of said curve.
Claim 4
Dependent Claim
37 words
A signaling circuit as claimed in claim 1, in which said further counter is reversible to produce a digital word on the reverse cycle which is a mirror image of the word produced on the forward cycle.
Claim 5
Dependent Claim
213 words
A dual tone multi-frequency generator for telephone usage comprising a multiple button keyboard wherein operation of any selected button generates a first digital word representing a high frequency tone and a second digital word representing a low frequency tone, a basic frequency clock generative of pulses at a clock frequency rate to a high frequency tone path and a low frequency tone path, a variable modulo divider in each path for dividing the clock frequency rate at respective selected high and low rates responsive to paired signals from the operated button for transmission along the respective paths, a fixed-count reversible divider in each path for emitting stream of pulses to each path based on selected high and low rates divided by said fixed count in each path, a programmable logic array in each path pulsed by the respective stream of pulses to produce binary digital words in delta modulation representing changes in an approximated sine wave at the respective high and low frequency tones, and in which each said fixed-count divider produces binary signals representing one quadrant of a sine wave in traverse thereof, and each said counter automatically reverses at the end of the fixed count to produce a second quadrant of the sine wave during a reverse tranverse of said counter.
Claim 6
Dependent Claim
213 words
A dual tone multi-frequency generator for telephone usage comprising a multiple button keyboard wherein operation of any selected button generates a first digital word representing a high frequency tone and a second digital word representing a low frequency tone, a basic frequency clock generative of pulses at a clock frequency rate to a high frequency tone path and a low frequency tone path, a variable modulo divider in each path for dividing the clock frequency rate at respective selected high and low rates responsive to paired signals from the operated button for transmission along the respective paths, a fixed-count reversible divider in each path for emitting stream of pulses to each path based on selected high and low rates divided by said fixed count in each path, a programmable logic array in each path pulsed by the respective stream of pulses to produce binary digital words in delta modulation representing changes in an approximated sine wave at the respective high and low frequency tones, and in which each said fixed-count divider produces binary signals representing one quadrant of a sine wave in traverse thereof, and each said counter automatically reverses at the end of the fixed count to produce a second quadrant of the sine wave during a reverse tranverse of said counter.
Claim 7
Dependent Claim
52 words
A generator as claimed in claim 4, in which each said logic array comprises a plurality of gates with input connections to said gates being programmable to produce a bit stream for digital synthesis of a high frequency and a low frequency sine wave at the respective high and low frequency rate.
Claim 8
Dependent Claim
18 words
A generator as claimed in claim 4, wherein each said fixed count divider comprises a binary digital counter.
Claim 9
Dependent Claim
38 words
A generator as claimed in claim 6, wherein there is means responsive to the absence of one of said paired signals from an operated button for preventing high frequency pulses from reaching said high and said low paths.
Claim 10
Dependent Claim
37 words
A generator as claimed in claim 7, wherein each said logic array also includes means responsive to an improper one of said paired signals from an operated button for inactivating the variable modulo counter for both paths.
Claim 11
Independent Claim
248 words
A device for digitally creating a signal of a predetermined frequency from a high group of frequencies and a singal of predetermined frequency from a low group of frequencies, responsive to operation of a selected manual input member of a plurality of input members, said device comprising means for developing a base frequency signal at a rate greater than any of said high frequency signals, a plurality of frequency dividers for said low group and a second plurality of frequency dividers for said high group, with each of said dividers activatable to divide said base signal frequency by a different count, means for activating a divider for said high group and a divider for said low group responsive to the selective operation of one member to produce a high group signal and a low group signal, means for counting recurrences of the high group signal and the low group signal by the same fixed count to produce a plurality of pulsed signals at a low rate and at a high rate, a first logic array for signals of said low rate and a second logic array for signals of said high rate, said logic array responsive to said pulsed signals at said high rate and said low rate for revising a programmed binary digital word determinative of changes in amplitude of a sine wave at said high rate and at said low rate for delta modulating a sine curve for the high group and for the low group.
Claim 12
Independent Claim
248 words
A device for digitally creating a signal of a predetermined frequency from a high group of frequencies and a singal of predetermined frequency from a low group of frequencies, responsive to operation of a selected manual input member of a plurality of input members, said device comprising means for developing a base frequency signal at a rate greater than any of said high frequency signals, a plurality of frequency dividers for said low group and a second plurality of frequency dividers for said high group, with each of said dividers activatable to divide said base signal frequency by a different count, means for activating a divider for said high group and a divider for said low group responsive to the selective operation of one member to produce a high group signal and a low group signal, means for counting recurrences of the high group signal and the low group signal by the same fixed count to produce a plurality of pulsed signals at a low rate and at a high rate, a first logic array for signals of said low rate and a second logic array for signals of said high rate, said logic array responsive to said pulsed signals at said high rate and said low rate for revising a programmed binary digital word determinative of changes in amplitude of a sine wave at said high rate and at said low rate for delta modulating a sine curve for the high group and for the low group.
Claim 13
Dependent Claim
92 words
A device as claimed in claim 9, in which the count of each of said further counting means comprises a plurality of time intervals in a sine wave to produce four digital words during the intervals defining a sine wave with said words comprising essentially the same combination of binary bits, the bits of the second and fourth words being reversed from the first and third words, and in which there are means for reversing the polarity of the bits comprising said second and third words from said first and fourth words.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-08-28 | 1982-02-27 | 1982-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-08-28 | 1986-02-27 | 1986-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-08-28 | 1990-02-27 | 1990-08-29 | $7700.00 | Window Closed / Lapsed |