Digital tone signal generator

Claim 2

A digital signal generator comprising, digital counter means for cyclically generating pulses in response to an input signal, means for varying the period of the cycle of said digital counter means as a function of the input signal, and shift register means responsive to the pulses generated by said digital counter means for generating digital output signals having a fundamental frequency component representative of said input signal.

Claim 3

The digital signal generator recited in claim 1 including input means for supplying a plurality of input signals, each of said input signals exhibiting a different frequency.

Claim 4

The digital signal generator recited in claim 1 including summing means connected to said shift register means to receive the digital output signals generated thereby, and decoding means connected to receive said input signal for operation thereon and application to said counter means.

Claim 5

A digital signal generator comprising, first and second counter circuits for cyclically counting to first and second counts respectively in response to separate input signals, each of said first and second counter circuits including means for varying the period of the counting cycle as a function of said input signals, each of said counter circuits providing output pulses for each cycle upon achieving said first and second counts, first and second shift register circuits responsive to the output pulses from said first and second counter circuits respectively for being set to a prescribed bit configuration, each of said first and second shift register circuits providing an output voltage level from each stage thereof as a function of said bit configuration, and first and second voltage summing circuits for summing the output voltage level from each stage of said first and second shift register circuits for producing digital signals having fundamental frequency components representing each of said input signals.

Claim 6

A digital signal generator comprising, first and second counter circuits for cyclically counting to first and second counts respectively in response to separate input signals, each of said first and second counter circuits including means for varying the period of the counting cycle as a function of said input signals, each of said counter circuits providing output pulses for each cycle upon achieving said first and second counts, first and second shift register circuits responsive to the output pulses from said first and second counter circuits respectively for being set to a prescribed bit configuration, each of said first and second shift register circuits providing an output voltage level from each stage thereof as a function of said bit configuration, and first and second voltage summing circuits for summing the output voltage level from each stage of said first and second shift register circuits for producing digital signals having fundamental frequency components representing each of said input signals.

Claim 7

The digital signal generator recited in claim 2 further including means for combining the digital signals from said first and second voltage summing circuits for producing one composite output signal representing both of said input signals.

Claim 8

The digital signal generator 4 wherein said first and second shift register circuits include means for inhibiting certain bit configurations for producing said digital signals with relatively high fundamental frequency components and relatively low harmonic frequency components.

Claim 9

The digital signal generator 4 wherein said first and second shift register circuits include means for inhibiting certain bit configurations for producing said digital signals with relatively high fundamental frequency components and relatively low harmonic frequency components.

Claim 10

The digital signal generator recited in claim 4 further including means for detecting more than one input signal, and means for inhibiting change in the bit configuration of said shift register circuits upon detection of more than one input signal by said means for detecting.

Claim 11

The digital signal generator recited in claim 4 wherein said first and second counter circuits each include control circuitry for enabling each counter to be reset to a predetermined logic state upon detection of said first and second counts.

Claim 12

The digital signal generator recited in claim 8 wherein one of said counters includes more stages than the other counter thereby providing said output pulses at different rates whereby relatively high and low frequency signals are generated at the output of said summing circuits.

Claim 13

The digital signal generator recited in claim 4 including means for supplying a plurality of input signals of different frequencies, decoding means connected to receive said input signals and to apply decoded signals to each of said first and second counter means.