US4546487A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Auto ranging counter
Assignee: Intersil Corp
•
Filing: 1983-12-30
•
Granted: 1985-10-08
•
Expires: 2003-12-30
Abstract
Abstract At the inception of a time interval whose duration is to be measured, pulses whose rate may be varied are applied to a first counter. A second counter controls the rate of the pulses applied to the first counter. An overflow sensing circuit is connected to the output of the first counter for, in response to each overflow signal at the output of the first counter, incrementing the second counter which then causes pulses having a new rate to be applied to the first counter and for, concurrently, presetting the counter to a new count. The new rate is equal to 1/N the old rate and the new count is equal to 1/N the count in the first control prior to the overflow. The elapsed time information in the circuit is therefore always valid.
Inventors
- 👤 Paul N. Dackow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:00
CPC Classifications
G; G01; G01R; G01R15/00; G01R15/08; G01R15/09; G04; G04F; G04F10/00; G04F10/04
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
135 words
The combination comprising: first and second counters; timing means for producing pulses whose frequency may be altered; means for selectively applying said pulses to said first counter; means responsive to the count in said second counter coupled to said timing means for decreasing the frequency of the pulses produced by said timing means by a factor of 1/N each time the count in said second counter increases where N is a positive integer greater than 1; and overflow sensing means coupled between said first and second counters responsive to an overflow signal at an output of said first counter for incrementing the count in said second counter and for presetting the count in said first counter to a new count which is equal to 1/N the count in the first counter prior to its overflow.
Claim 2
Dependent Claim
135 words
The combination comprising: first and second counters; timing means for producing pulses whose frequency may be altered; means for selectively applying said pulses to said first counter; means responsive to the count in said second counter coupled to said timing means for decreasing the frequency of the pulses produced by said timing means by a factor of 1/N each time the count in said second counter increases where N is a positive integer greater than 1; and overflow sensing means coupled between said first and second counters responsive to an overflow signal at an output of said first counter for incrementing the count in said second counter and for presetting the count in said first counter to a new count which is equal to 1/N the count in the first counter prior to its overflow.
Claim 3
Dependent Claim
31 words
The combination as claimed in claim 1 wherein said timing means is an oscillator whose frequency is varied as a function of the value of the count in said second counter.
Claim 4
Dependent Claim
86 words
The combination as claimed in claim 1 wherein said timing means includes an oscillator, a frequency divider and a multiplexer, wherein said frequency divider has an input coupled to said oscillator and has a plurality of outputs for producing succeeding lower frequency signal, and wherein said multiplexer is coupled to the oscillator and to the frequency divider outputs and is responsive to the count in said second counter for producing pulses at its output whose rate are a function of the count in said second counter.
Claim 5
Dependent Claim
16 words
The combination as claimed in claim 2 wherein said first and second counters are binary counters.
Claim 6
Dependent Claim
64 words
The combination as claimed in claim 1 wherein said first counter includes R binary stages, where R is a positive integer greater than 1, and wherein said second counter includes M stages, where M is a positive integer greater than 1, and wherein a particular stage of said first counter is preset each time said first counter overflows and said second counter is incremented.
Claim 7
Dependent Claim
139 words
An auto-ranging counting system comprising: counting means adapted to received pulses; controllable timing means for producing at its output pulses whose rate may be altered; means for selectively applying said pulses to said counting means; and means responsive to an overflow condition at an output of said counting means for altering, in response to an overflow signal, the rate of the pulses produced by the controllable timing means, the new rate being equal to 1/N the rate of the pulses applied to the counting means immediately prior to the overflow condition, and said means responsive to an overflow condition also including means coupled to said counting means for setting, in response to an overflow signal, the count of said counting means to a value equal to 1/N the count in the counting means immediately prior to the overflow condition.
Claim 8
Dependent Claim
139 words
An auto-ranging counting system comprising: counting means adapted to received pulses; controllable timing means for producing at its output pulses whose rate may be altered; means for selectively applying said pulses to said counting means; and means responsive to an overflow condition at an output of said counting means for altering, in response to an overflow signal, the rate of the pulses produced by the controllable timing means, the new rate being equal to 1/N the rate of the pulses applied to the counting means immediately prior to the overflow condition, and said means responsive to an overflow condition also including means coupled to said counting means for setting, in response to an overflow signal, the count of said counting means to a value equal to 1/N the count in the counting means immediately prior to the overflow condition.
Claim 9
Dependent Claim
108 words
The auto-ranging counting system as claimed in claim 6 wherein said controllable timing means includes an oscillator producing output signals of a fixed frequency, fc, and a frequency divider circuit having an input connected to said oscillator for receiving said fixed frequency signal, said frequency divider having X succeeding outputs, each succeeding output of said frequency divider for producing an output signal whose frequency is 1/N the frequency of the preceding output; and wherein said controllable timing means also includes multiplexing means coupled to said oscillator and frequency divider for, in response to a control signal, producing a selected one of said frequency signals at its said output.
Claim 10
Dependent Claim
83 words
The auto ranging counter as claimed in claim 7 wherein said means responsive to an overflow condition includes a range counter responsive to an overflow at the output of said counting means, said range counter being incremented by a count each time said counting means overflows, and said range counter being coupled to said multiplexer, for, in response to each incremented condition, applying a signal to said multiplexer for selecting a succeeding, lower, frequency than the previous frequency applied to said counting means.
Claim 11
Dependent Claim
133 words
The combination comprising: first and second counters; timing means for producing pulses whose frequency may be altered; means for selectively applying said pulses to said first counter; means responsive to the count in said second counter coupled to said timing means for decreasing the frequency of the pulses produced by said timing means from a frequency f 1 to a frequency f 2 each time the count in said second counter increases; and overflow sensing means coupled between said first and second counters responsive to an overflow signal at an output of said first counter for incrementing the count in said second counter and for presetting the count in said first counter to a new count; where the new count times 1/f 2 is equal to the old count times 1/f 1 .
Claim 12
Dependent Claim
133 words
The combination comprising: first and second counters; timing means for producing pulses whose frequency may be altered; means for selectively applying said pulses to said first counter; means responsive to the count in said second counter coupled to said timing means for decreasing the frequency of the pulses produced by said timing means from a frequency f 1 to a frequency f 2 each time the count in said second counter increases; and overflow sensing means coupled between said first and second counters responsive to an overflow signal at an output of said first counter for incrementing the count in said second counter and for presetting the count in said first counter to a new count; where the new count times 1/f 2 is equal to the old count times 1/f 1 .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-10-07 | 1989-04-08 | 1989-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-10-07 | 1993-04-08 | 1993-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-10-07 | 1997-04-08 | 1997-10-08 | $7700.00 | Window Closed / Lapsed |