Fast scan/set testable latch using two levels of series gating with one current source

Claim 1

In interconnection to and functional augmentation of a two-level-series-gated one-current-source feedback latch circuit employing one current source supplying current, serially connected to a first-level current-switch responisve to a received system clock signal for steering said current either to maintain, as a feedback current, said latch circuit in a set or clear state or else steering said current to one second-level current-switch responsive to a received system data signal for steering current received of said first-level current switch to either a clear Q or else to a set Q signal outputs of said latch circuit in order to respectively set or clear said latch circuit, a circuit apparatus interconnected to said feedback latch circuit for making said feedback latch fircuit functionally responsive to received scan/set data and scan/set clock signals thereby making said feedback latch circuit scan/set testable, said circuit apparatus comprising: a first-level gating-circuit constituting a substitutionary inverting one-half of said first-level current switch while a normal inverting one-half of said first-level current switch is inactive due to absence of said received system clock signal, said first-level gating-circuit connected intermediary said current source and another second-level current switch, said first gating-circuit being interactive with the normal non-inverting one-half of said first-level current-switch, which said normal non-inverting one-half of said first-level current-switch is also connected to said current source and upon said first-level, in order to sufficiently form by said being interactive a complete current-switch upon said first-level, WHEREIN said complete current-switch is responsive to said scan/set clock signal for IF said scan/set clock signal is true THEN steering said current received of said current source to said another second-level current-switch ELSE IF said scan/set clock signal is false THEN steering no current to said another second-level current-switch and doing naught but presenting but a small, non-interfering, impedance to the operation of said normally constituted first-level current-switch; and said another second-level current switch is connected between said first-level gating circuit and said signal outputs of said feedback latch, comprising collector-dotted connections to each said clear Q and set Q signal outputs of said feedback latch circuit, for IF supplied with a current steered from said complete current-switch THEN, responsively to the binary state of a received said scan/set data signal, IF said scan/set data input signal is true THEN steering said current to said clear Q signal output of said feedback latch circuit sufficient to set said feedback latch circuit ELSE IF said scan/set data input signal is false THEN steering said current to said set Q signal output of said feedback latch circuit sufficient to clear said feedback latch circuit, ELSE IF not supplied with a current steered from said complete current-switch THEN doing naught but presenting a small capacitance to said set Q and said clear Q signal outputs of said feedback latch circuit.