US4546272A
Expired / Lapsed
US
⏱️ 0.0 years remaining
ECL Circuit for forcibly setting a high level output
Assignee: Fujitsu Ltd
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Filing: 1983-05-27
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Granted: 1985-10-08
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Expires: 2003-05-27
Abstract
Abstract An ECL circuit includes a differential pair of transistors, a set transistor, and a set resistor connected between the emitters of the differential pair of transistors and the emitter of the set transistor. The output of the ECL circuit can be fixed securely to a "high" level only by applying a "high" level signal having the same level as the "high" level signal of the data input to the base of the set transistor.
Inventors
- 👤 Hirokazu Suzuki
- 👤 Masayuki Kokado
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 05:09
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K5/00; H03K5/22; H03K5/24
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
135 words
An emitter coupled logic circuit operatively connected to receive complementary signals and a set signal, and having an output terminal, comprising: a differential pair of transistors having emitters commonly connected, having bases for receiving the complementary signals, and having collectors; an impedance element operatively connected to the commonly connected emitters of said differential pair of transistors; a constant current source operatively connected to said impedance element; and a set transistor having an emitter operatively connected to said constant current source, having a base for receiving the set signal and having a collector operatively connected to the collector of one of said differential pair of transistors, the output terminal being operatively connected to the collector of one of the transistors forming said differential pair of transistors, for providing an output from said differential pair of transistors.
Claim 2
Dependent Claim
135 words
An emitter coupled logic circuit operatively connected to receive complementary signals and a set signal, and having an output terminal, comprising: a differential pair of transistors having emitters commonly connected, having bases for receiving the complementary signals, and having collectors; an impedance element operatively connected to the commonly connected emitters of said differential pair of transistors; a constant current source operatively connected to said impedance element; and a set transistor having an emitter operatively connected to said constant current source, having a base for receiving the set signal and having a collector operatively connected to the collector of one of said differential pair of transistors, the output terminal being operatively connected to the collector of one of the transistors forming said differential pair of transistors, for providing an output from said differential pair of transistors.
Claim 3
Dependent Claim
58 words
An emitter coupled logic circuit as defined in claim 1, wherein said differential pair of transistors have a first threshold voltage level, wherein said set transistor has a second threshold voltage level, and wherein the second threshold voltage level of said set transistor is made smaller than the first threshold voltage level of said differential pair of transistors.
Claim 4
Dependent Claim
27 words
An emitter coupled logic circuit as defined in claim 1, wherein the collector of said set transistor is an output terminal of said emitter coupled logic circuit.
Claim 5
Dependent Claim
179 words
An emitter coupled logic circuit operatively connected to receive a first input signal, a second input signal which is a complement of the first input signal and a set signal, and having an output terminal, comprising: a first differential transistor having a base operatively connected to receive the first input signal, having an emitter and having a collector; a second differential transistor having a base operatively connected to receive the second input signal, having an emitter operatively connected to the emitter of said first differential transistor at a node, and having a collector operatively connected to the output terminal for providing an output from said second differential transistor; a set transistor having a base operatively connected to receive the set signal, having a collector operatively connected to the collector of said first differential transistor, and having an emitter; a set resistor having a first terminal operatively connected to said node and having a second terminal operatively connected to the emitter of said set transistor; and a constant current source operatively connected to said second terminal of said set resistor.
Claim 6
Dependent Claim
179 words
An emitter coupled logic circuit operatively connected to receive a first input signal, a second input signal which is a complement of the first input signal and a set signal, and having an output terminal, comprising: a first differential transistor having a base operatively connected to receive the first input signal, having an emitter and having a collector; a second differential transistor having a base operatively connected to receive the second input signal, having an emitter operatively connected to the emitter of said first differential transistor at a node, and having a collector operatively connected to the output terminal for providing an output from said second differential transistor; a set transistor having a base operatively connected to receive the set signal, having a collector operatively connected to the collector of said first differential transistor, and having an emitter; a set resistor having a first terminal operatively connected to said node and having a second terminal operatively connected to the emitter of said set transistor; and a constant current source operatively connected to said second terminal of said set resistor.
Claim 7
Dependent Claim
77 words
An emitter coupled logic circuit, operatively connectable to receive a reset signal, as defined in claim 4, further comprising a reset transistor having a base operatively connected to receive the reset signal, having an emitter operatively connected to said second terminal of said set resistor and having a collector operatively connected to the collector of said second differential transistor, wherein said collector of said reset transistor functions as an output terminal of the emitter coupled logic circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-10-07 | 1989-04-08 | 1989-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-10-07 | 1993-04-08 | 1993-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-10-07 | 1997-04-08 | 1997-10-08 | $7700.00 | Window Closed / Lapsed |