US3885169A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Storage-processor element including a bistable circuit and a steering circuit
Assignee: AT&T Inc
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Filing: 1972-11-15
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Granted: 1975-05-20
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Expires: 1992-11-15
Abstract
Abstract Disclosed is a storage-processor element, designed so that groups of such elements can be interconnected into threshold logic circuits. Each element is arranged to decide which one of a pair of double-rail input signals has a higher potential and to store the result of that decision. Information read out of storage directs a unit of current to one or the other of two output busses. A threshold logic adder circuit and a threshold logic two''scomplement circuit use combinations of the storage-processor elements.
Inventors
- 👤 John Donnell Heightley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:47
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/0813; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885; G06F2207/00; G06F2207/38; G06F2207/48; G06F2207/4802; G06F2207/4818
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
174 words
A storage-processor element comprising a flip-flop circuit having first and second input terminals and first and second output terminals, first and second input circuit means respectively for coupling double-rail input signals to the first and second input terminals, the flip-flop circuit being constrained to one of two stable states in response to the input signals and indicating the assumed state at the first and second output terminals, first and second charge storage devices retaining previously determined charge conditions independent of the state to which the flip-flop circuit is being constrained by the input signals, first and second asymmetrically conducting devices respectively coupling signals representing the assumed state of the flipflop from the first and second output terminals to the first and second charge storage means for storing the assumed state of the flip-flop circuit as quantIties of charge, first and second busses, and means for converting the charge stored in the first and second charge storage means into a predetermined magnitude of current that is steered to one or the other of the busses.
Claim 2
Dependent Claim
174 words
A storage-processor element comprising a flip-flop circuit having first and second input terminals and first and second output terminals, first and second input circuit means respectively for coupling double-rail input signals to the first and second input terminals, the flip-flop circuit being constrained to one of two stable states in response to the input signals and indicating the assumed state at the first and second output terminals, first and second charge storage devices retaining previously determined charge conditions independent of the state to which the flip-flop circuit is being constrained by the input signals, first and second asymmetrically conducting devices respectively coupling signals representing the assumed state of the flipflop from the first and second output terminals to the first and second charge storage means for storing the assumed state of the flip-flop circuit as quantIties of charge, first and second busses, and means for converting the charge stored in the first and second charge storage means into a predetermined magnitude of current that is steered to one or the other of the busses.
Claim 3
Dependent Claim
29 words
A storage-processor element in accordance with claim 1 further comprising means connecting with the converting means for disabling the converting means from steering current to either of the busses.
Claim 4
Dependent Claim
71 words
A storage-processor element in accordance with claim 1 wherein the flip-flop circuit comprises a pair of transistors cross-coupled for alternative conduction, the first and second input circuit means each separately couples a different input signal to a different input of the flip-flop circuit, the first and second charge storage means include parasitic base-collector capacitance of a pair of emitter-follower connected transistors, and the converting means include an emitter-coupled pair of transistors.
Claim 5
Dependent Claim
47 words
A storage-processor element in accordance with claim 3 wherein the first and second input circuits each comprise a common-collector connected transistor of an opposite conductivity type than the transistors of the flip-flop, the common-collector transistors having emitter electrodes connected respectively to the first and second input terminals.
Claim 6
Dependent Claim
27 words
A storage-processor element in accordance with claim 3 further comprising means connecting with the emitters of the emitter-coupled pair of transistors for disabling the current steering means.
Claim 7
Dependent Claim
142 words
A storage-processor element comprising a bistable circuit for producing at first and second output terminals signals representing the state of the circuit, means for coupling input signals to the circuit, first and second charge storage devices, first and second switching devices for coupling respectively the first and second output terminals to the first and second charge storage devices to store therein the state of the circuit as quantities of charge, means for steering a predetermined magnitude of current alternatively to one or another of first and second storage-processor element output terminals in response to the charge stored in the first and second charge storage devices, and means for biasing the first and second switching devices to cutoff for retaining the charge on the first and second charge storage devices for a predetermined duration after the state of the bistable circuit is terminated.
Claim 8
Dependent Claim
142 words
A storage-processor element comprising a bistable circuit for producing at first and second output terminals signals representing the state of the circuit, means for coupling input signals to the circuit, first and second charge storage devices, first and second switching devices for coupling respectively the first and second output terminals to the first and second charge storage devices to store therein the state of the circuit as quantities of charge, means for steering a predetermined magnitude of current alternatively to one or another of first and second storage-processor element output terminals in response to the charge stored in the first and second charge storage devices, and means for biasing the first and second switching devices to cutoff for retaining the charge on the first and second charge storage devices for a predetermined duration after the state of the bistable circuit is terminated.
Claim 9
Dependent Claim
37 words
An element in accordance with claim 6 wherein the bistable circuit comprises a pair of transistors cross-coupled for alternative conduction, the coupling means include separate paths for coupling complementary signals to different terminals of the bistable circuit.
Claim 10
Dependent Claim
23 words
A storage-processor element in accordance with claim 6 further comprising means connecting with the current steering means for disabling the current steering means.
Claim 11
Dependent Claim
66 words
An element in accordance with claim 7 wherein the first and second charge storage devices comprise parasitic capacitances of a pair of emitter-follower connected transistors, and the steering means include an emitter-coupled pair of transistors each having a base electrode connected with a different emitter of the emitter-follower connected transistors and each having a collector electrode connected with a different one of the element output terminals.
Claim 12
Dependent Claim
27 words
A storage-processor element in accordance with claim 9 further comprising means connecting with the emitters of the emitter-coupled pair of transistors for disabling the current steering means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-19 | 1978-11-18 | 1979-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-19 | 1982-11-18 | 1983-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-19 | 1986-11-18 | 1987-05-20 | $7700.00 | Window Closed / Lapsed |