Semiconductor storage apparatus

Claim 2

In semiconductor apparatus adapted for storing and transferring information signals wherein each of a plurality of storage cells is coupled through asymmetrically conducting means to at least one information conduction path, the improvement which comprises: a storage cell including: first and second bipolar transistors, each having an emitter, base, and collector; the emitter of each transistor being connected to the emitter of the other transistor; first and second internal circuit nodes; a first pair of resistive means, one of which is connected between the collector of the first transistor and the first node and the other of which is connected between the first node and the base of the second transistor; a second pair of resistive means, one of which is connected between the collector of the second transistor and the second node and the other of which is connected between the second node and the base of the first transistor; a third pair of resistive means coupling separately the collector of each transistor to a common terminal adapted for coupling to a source of electric power; and another resistive means connected between the asymmetrically conducting means and the first node.

Claim 3

Apparatus as recited in claim 3 wherein the asymmetrically conducting means comprises a diode.

Claim 4

Apparatus as recited in claim 3 wherein the impedance presented by the another resistive means is at least as great as the impedance presented by the resistive means connected between said first node and the collector of the first transistor.

Claim 5

Apparatus as recited in claim 3 wherein the ratio of the impedance presented by the another resistive means to the impedance presented by the resistive means connected between said first node and the collector of the first transistor is between about 1.5 and 2.0.

Claim 6

Apparatus as recited in claim 6 wherein the ratio of the impedance presented by the another resistive means to the impedance presented by the resistive means connected between said first node and the collector of the first transistor is no greater than about four.

Claim 7

In apparatus of the type adapted for storing and transferring information and comprising a matrix of storage cells interconnected by means forming a first plurality of word line conduction paths and means forming a second plurality of pairs of digit line conduction paths and wherein the cells in a given row of the matrix are connected to a common one of the plurality of word line conduction paths and the cells in a given column are connected to a common pair of the second plurality of pairs of digit line conduction paths through a corresponding plurality of pairs of asymmetrically conducting means in such a manner that the amplitudes of the reading and writing signals from and into said cells are essentially independent of standby power levels in the cells, the improvement being an improved storage cell which comprises: first and second bipolar transistors, each having An emitter, base, and collector; the emitter of each transistor being connected to the emitter of the other transistor; first and second internal circuit nodes; a first pair of resistive means, one of which is connected between the collector of the first transistor and the first node and the other of which is connected between the first node and the base of the second transistor; a second pair of resistive means, one of which is connected between the collector of the second transistor and the second node and the other of which is connected between the second node and the base of the first transistor; a third pair of resistive means coupling separately the collector of each transistor to a common terminal adapted for coupling to a source of electric power; and a fourth pair of resistive means, one of which is connected between the first node and one of the asymmetrically conducting means and the other of which is connected between the second node and the other asymmetrically conducting means of one of said pairs of asymmetrically conducting means.

Claim 8

Apparatus as recited in claim 8 wherein an asymmetrically conducting means comprises a diode.

Claim 9

Apparatus as recited in claim 9 wherein the pairs of diodes are poled so that current flowing in the forward-biased direction through the diodes tends to turn on the cross-coupled transistor into whose base it flows.

Claim 10

Storage apparatus as recited in claim 9 further characterized in that the diode includes only two terminals, one of which is connected to the cell, and the other of which is connected to a digit line.

Claim 11

Storage apparatus as recited in claim 11 further characterized in that the anode of each coupling diode is connected to a digit line and the cathode of each coupling diode is connected to the cell.

Claim 12

Storage apparatus as recited in claim 12 further characterized in that the anode of each coupling diode is connected to a digit line and the cathode of each coupling diode is connected to the base of a transistor within a cell through resistance means.

Claim 13

Apparatus as recited in claim 9 additionally comprising: a first plurality of circuit means, each of which is connected to at least one of said word line conduction paths, and each of which includes means in response to a control signal for reducing the voltage on the word line conduction path to which it is connected sufficiently to cause a detectable amount of current to flow from at least one of said digit lines through at least one diode of one of said pairs of coupling diodes into at least one of said cells.

Claim 14

Apparatus as recited in claim 9 additionally comprising: a first plurality of circuit means each of which is connected to at least one of said word line conduction paths, and each of which includes means in response to a control signal for changing the voltage on the word line conduction path to which it is connected; and a second plurality of circuit means, each of which is connected to at least one pair of said pairs of digit line conduction paths, and each of which includes means in response to a control signal for selectively energizing one conduction path of the pair of conduction paths to which it is connected sufficiently to cause the storing of a signal in the cell to which the energized digit line and the word line having the changed voltage are coupled; so that information thereby is written into the cell via a current amplitude which is essentially independent of the standby current amplitudes within the cell.