US4626293A
Expired / Lapsed
US
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Method of making a high voltage DMOS transistor
Assignee: Alcatel Lucent NV
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Filing: 1984-06-27
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Granted: 1986-12-02
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Expires: 2004-06-27
Abstract
Abstract A process for manufacturing a high voltage DMOS (Deep Diffusion Metal Oxide Semiconductor) transistor includes a first ion implantation and drive-in step to form a P-well in a N-substrate, and a second such step to form a N+ region in this well and a channel between this region and the substrate and under a polysilicon gate which is covered with a silicon nitride layer during the first step. By the presence of the latter layer pitting of the gate is prevented and no leakage paths are formed between source and drain.
Inventors
- 👤 Gustaaf Schols
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:37
CPC Classifications
H; H10; H10K; H10K99/00; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/694; H10P14/6943; H10P14/69433; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/65; H10P32/00; H10P32/10; H10P32/14; H10P32/1404; H10P32/1406; H10P32/17; H10P32/171; H10P76/00; H10P76/40; Y; Y10; Y10S; Y10S148/00; Y10S148/082
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
161 words
A process for making a semiconductor device comprising the steps of: providing a substrate of a first conductivity type; covering said substrate with an oxide layer; forming a polysilicon gate on said oxide layer; forming an opening in said oxide layer; subjecting said substrate to a first predeposition of impurity material of a second conductivity type through said opening; subjecting said substrate to a first diffusion drive-in operation to form a well of said second conductivity type therein through said opening; subjecting said substrate to a second predeposition and second diffusion drive-in steps of impurity material to form a region in said well through said opening separated from the boundary of said well by a channel zone, said channel zone being formed under said polysilicon gate; covering said polysilicon gate by a silicon nitride layer during at least said first drive-in step; and wherein said region forms the source of said device and said substrate forms the drain of said device.
Claim 2
Dependent Claim
161 words
A process for making a semiconductor device comprising the steps of: providing a substrate of a first conductivity type; covering said substrate with an oxide layer; forming a polysilicon gate on said oxide layer; forming an opening in said oxide layer; subjecting said substrate to a first predeposition of impurity material of a second conductivity type through said opening; subjecting said substrate to a first diffusion drive-in operation to form a well of said second conductivity type therein through said opening; subjecting said substrate to a second predeposition and second diffusion drive-in steps of impurity material to form a region in said well through said opening separated from the boundary of said well by a channel zone, said channel zone being formed under said polysilicon gate; covering said polysilicon gate by a silicon nitride layer during at least said first drive-in step; and wherein said region forms the source of said device and said substrate forms the drain of said device.
Claim 3
Dependent Claim
19 words
A process in accordance with claim 1 wherein; said first drive-in step is carried out in a nitrogen atmosphere.
Claim 4
Dependent Claim
18 words
A process in accordance with claim 1 wherein said first predeposition step is carried out by ion implantation.
Claim 5
Dependent Claim
30 words
A process in accordance with claim 1 wherein: said first diffusion drive-in is performed at a high temperature of about 1200° C. for a long duration of about 50 hours.
Claim 6
Dependent Claim
25 words
A process in accordance with claim 1 wherein: said first conductivity type is N type conductivity; and said second conductivity type is P type conductivity.
Claim 7
Dependent Claim
21 words
A process in accordance with claim 4 where said second conductivity type and said impurity material are of P type conductivity.
Claim 8
Dependent Claim
165 words
A process for making a semiconductor device comprising the steps of: providing a substrate of a first conductivity type; covering said substrate with an oxide layer; forming a polysilicon gate on said oxide layer; forming a first and a second opening in said oxide layer; subjecting said substrate to a first predeposition of impurity material of a second conductivity type through said first opening; subjecting said substrate to a first diffusion drive-in operation to form a well of said second conductivity type therein through said first opening; subjecting said substrate to a second predeposition and second diffusion drive-in steps of impurity material through said second opening to form a region separated from the boundary of said well by a channel zone, said channel zone being formed under said polysilicon gate; covering said polysilicon gate by a silicon nitride layer during at least said first drive-in step; and wherein said region forms the source of said device and said well forms the drain of said device.
Claim 9
Dependent Claim
165 words
A process for making a semiconductor device comprising the steps of: providing a substrate of a first conductivity type; covering said substrate with an oxide layer; forming a polysilicon gate on said oxide layer; forming a first and a second opening in said oxide layer; subjecting said substrate to a first predeposition of impurity material of a second conductivity type through said first opening; subjecting said substrate to a first diffusion drive-in operation to form a well of said second conductivity type therein through said first opening; subjecting said substrate to a second predeposition and second diffusion drive-in steps of impurity material through said second opening to form a region separated from the boundary of said well by a channel zone, said channel zone being formed under said polysilicon gate; covering said polysilicon gate by a silicon nitride layer during at least said first drive-in step; and wherein said region forms the source of said device and said well forms the drain of said device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1989-12-01 | 1990-06-02 | 1990-12-02 | $2000.00 | Window Closed / Lapsed |
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