Drain triggered N-channel non-volatile memory

Claim 2

An electrically alterable non-volatile memory for storing information comprising: an array of electrically alterable non-volatile memory elements arranged in a plurality of rows and a plurality of columns, each said non-volatile memory element includes a P-doped semiconductor substrate having first and second N-doped regions spaced apart, an insulation layer over said substrate overlaying a path from said first N-doped region to said second N-doped region, a conductive layer on top of said insulation layer overlaying a path from said first N-doped region to at least a predetermined distance from said second N-doped region, said insulation layer between said substrate and said conductive layer having a thickness to exhibit a variable threshold characteristic upon application of a first polarization voltage between said conductive layer and said substrate to cause an N-type depletion mode channel to form in said substrate extending from said first N-doped region to only a predetermined distance from said second N-doped region, means for writing information into said array, means for reading information from said array including, first means for holding the potential of the conductive layer of each memory element in said array at substantially the potential of its respective substrate, second means for selecting one row of said array in response to address signals, third means for holding the potential of said second region of each memory element in said non-selected rows less than a predetermined positive potential with respect to its respective substrate to prevent the formation of a depletion region in each memory element from extending from said second N-doped region to at least said predetermined distance into said substrate, fourth means for applying a first voltage to the second region of each memory element in said selected row, said first voltage more positive than said predetermined positive potential and being of sufficient magnitude to form a depletion region in each memory element extending from said second N-doped region to at least said predetermined distance into said substrate towards said first region to intersect with said depletion mode channel at times said depletion mode channel is present to enable conduction between said first and second N-doped regions, and means for sensing the conduction of current from said second region to said first region of each memory element in said selected row.

Claim 3

The electrically alterable non-volatile memory of claim 1 wherein said insulation layer includes a layer of silicon oxide and a layer of silicon nitride.

Claim 4

The electrically alterable non-volatile memory of claim 2 wherein said layer of silicon oxide has a first thickness t1 from said first N-doped region to a predetermined distance X from said second N-doped region and a second thickness t2 greater than said thickness t1 extending from said second N-doped region out said distance X to intersect with said layer of silicon oxide of thickness t1.

Claim 5

The electrically alterable non-volatile memory of claim 2 wherein said layer of nitride has a thickness t3.

Claim 6

The electrically alterable non-volatile memory of claim 1 wherein said conductive layer overlays a path from said first N-doped region to said second N-doped region.

Claim 7

The electrical alterable non-volatile memory of claim 1 wherein said conductive layer overlays a path from said first N-doped region to only a predetermined distance X from said second N-doped region.

Claim 8

The electrically alterable non-volatile memory of claim 1 wherein said substrate of each memory element is a common substrate to each other.

Claim 9

The electrically alterable non-volatile memory of claim 1 wherein said means for writing includes: fifth means for holding the potential of the conductive layer of each memory element in said array at substantially the potential of ground, sixth means for applying a positive voltage to the substrate of every memory element in said array to cause said N-type depletion mode channel to form in said substrate extending from said first N-doped region to only a predetermined distance from said second N-doped region, seventh means for selecting one row of said array in response to address signals and to a write control signal, said conductive layer in each memory element of each row of said array connected in common and coupled to said seventh means for selecting, said first region in each memory element of each column of said array connected in common, eighth means for applying a positive voltage to said first regions of each column in response to a first state of binary data desired to be stored, ninth means for applying substantially ground potential to said first regions of each column in response to a second state of binary data desired to be stored, said seventh means for selecting including tenth means for applying a positive voltage to said conductive layer in each memory element of said selected row to remove the previously formed depletion mode channel on those memory elements where its first region is at substantially ground potential.

Claim 10

The electrically alterable non-volatile memory of claim 1 wherein said means for writing includes: fifth means for holding the potential of the conductive layer of each memory element in said array at substantially ground potential, sixth means for selecting one row of said array in response to address signals and to a write control signal, seventh means for applying a positive voltage to the substrate of every memory element in said selected row to cause said N-type depletion mode channel to form in said substrate extending from said first N-doped region to only a predetermined distance from said second N-doped region, said conductive layer in each memory element of each row of said array connected in common and coupled to said sixth means for selecting, said first region in each memory element of each column of said array connected in common, eighth means for applying a positive voltage to said first regions of each column in response to a first state of binary data desired to be stored, ninth means for applying substantially ground potential to said first regions of each column in response to a second state of binary data desired to be stored, said sixth means for selecting including tenth means for applying a positive voltage to said conductive layer in each memory element of said selected row to remove the previously formed depletion mode channel on those memory elements where its first region is at substantially ground potential.

Claim 11

The electrically alterable non-volatile memory of claim 1 wherein said second region in each memory element of each row of said array are connected in common and coupled to said second means for selecting.

Claim 12

The electrically alterable non-volatile memory of claim 10 wherein said second means for selecting, third means for holding and fourth means for applying include a drain row decoder responsive to said address signals and a read control signal.

Claim 13

The electrically alterable non-volatile memory of claim 10 wherein said conductive layer in each memory element of each row of said array are connected in common and coupled to said first means for holding.

Claim 14

The electrically alterable non-volatile memory of claim 12 wherein said first region in each memory element of each column of said array are connected in common and coupled to said means for sensing.

Claim 15

The electrically alterable non-volatile memory of claim 12 wherein said first means for holding includes a gate row decoder responsive to a write control signal.

Claim 16

An electrically alterable non-volatile memory for storing information comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; each said memory cell includes a plurality of variable threshold transistors; each of said variable threshold transistors including a P-doped semiconductor substrate having first and second N-doped regions spaced apart, an insulation layer over said substrate overlaying a path from said first N-doped region to said second N-doped region, a conductive layer on top of said insulation layer overlaying a path from said first N-doped region to at least a predetermined distance from said second N-doped region, said insulation layer between said substrate and said conductive layer having a thickness to exhibit a variable threshold characteristic upon application of a first polarization voltage between said conductive layer and said substrate to cause an N-type depletion mode channel to form in said substrate extending from said first N-doped region to only a predetermined distance from said second N-doped region, means for writing information into said memory cells, means for reading information from said memory cells including, first means for holding the potential of the conductive layer of each variable threshold transistor at substantially the potential of its respective substrate, second means for selecting one row of memory cells in response to address signals, third means for holding the potential of said second region of each variable threshold transistor in said non-selected rows less than a predetermined positive potential with respect to its substrate to prevent the formation of a depletion region in each variable threshold transistor from extending from said second N-doped region to at least said predetermined distance into said substrate, fourth means for applying a first voltage to the second region of each variable threshold transistor in said selected row, said first voltage more positive than said predetermined positive potential and being of sufficient magnitude to form a depletion region in each variable threshold transistor extending from said second N-doped region to at least said predetermined distance into said substrate towards said first region to intersect with said depletion mode channel at times said depletion mode channel is present to enable conduction between said first and second N-doped regions, and means for sensing the conduction of current from said second region to said first region of at least two variable threshold transistors of each memory cell in said row.

Claim 17

An electrically alterable non-volatile memory for storing information comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; each said memory cell includes a plurality of variable threshold transistors; each of said variable threshold transistors including a P-doped semiconductor substrate having first and second N-doped regions spaced apart, an insulation layer over said substrate overlaying a path from said first N-doped region to said second N-doped region, a conductive layer on top of said insulation layer overlaying a path from said first N-doped region to at least a predetermined distance from said second N-doped region, said insulation layer between said substrate and said conductive layer having a thickness to exhibit a variable threshold characteristic upon application of a first polarization voltage between said conductive layer and said substrate to cause an N-type depletion mode channel to form in said substrate extending from said first N-doped region to only a predetermined distance from said second N-doped region, means for writing information into said memory cells, means for reading information from said memory cells including, first means for holding the potential of the conductive layer of each variable threshold transistor at substantially the potential of its respective substrate, second means for selecting one row of memory cells in response to address signals, third means for holding the potential of said second region of each variable threshold transistor in said non-selected rows less than a predetermined positive potential with respect to its substrate to prevent the formation of a depletion region in each variable threshold transistor from extending from said second N-doped region to at least said predetermined distance into said substrate, fourth means for applying a first voltage to the second region of each variable threshold transistor in said selected row, said first voltage more positive than said predetermined positive potential and being of sufficient magnitude to form a depletion region in each variable threshold transistor extending from said second N-doped region to at least said predetermined distance into said substrate towards said first region to intersect with said depletion mode channel at times said depletion mode channel is present to enable conduction between said first and second N-doped regions, and means for sensing the conduction of current from said second region to said first region of at least two variable threshold transistors of each memory cell in said row.

Claim 18

The electrically alterable non-volatile memory of claim 15 wherein said insulation layer includes a layer of silicon oxide and a layer of silicon nitride.

Claim 19

The electrically alterable non-volatile memory of claim 16 wherein said layer of silicon oxide has a first thickness t1 from said first N-doped region to a predetermined distance X from said second N-doped region and a second thickness t2 greater than said thickness t1 extending from said second N-doped region out said distance X to intersect with said layer of silicon oxide of thickness t1.

Claim 20

The electrically alterable non-volatile memory of claim 16 wherein said layer of nitride has a thickness of t3.

Claim 21

The electrically alterable non-volatile memory of claim 15 wherein said conductive layer overlays a path from said first N-doped region to said second N-doped region.

Claim 22

The electrical alterable non-volatile memory of claim 15 wherein said conductive layer overlays a path from said first N-doped region to only a predetermined distance X from said second N-doped region.

Claim 23

The electrically alterable non-volatile memory of claim 15 wherein said substrate of each variable threshold transistor of each memory cell is a common substrate to each other.

Claim 24

The electrically alterable non-volatile memory of claim 15, wherein said second region of each variable threshold transistor in each memory cell of each row are coupled together.

Claim 25

The electrically alterable non-volatile memory of claim 22 wherein said conductive layer of each variable threshold transistor in each memory cell of each row are coupled together.

Claim 26

The electrically alterable non-volatile memory of claim 23 wherein said first region of one variable threshold transistor in each memory cell of each column are coupled together.

Claim 27

The electrically alterable non-volatile memory of claim 24 wherein said first region of a second variable threshold transistor in each memory cell of each column are coupled together.